Hello everyone, I am running workloads on m5 where I am simulating 4 core CMP on m5 with shared L2. Cores are using alpha architecture.
I am interested in activity on the bus connecting L1 and L2. It seems to me that processor is not cycle accurate. In other words: During an L1 miss when it has to read data from L2. It accesses all 64 byte of data in one cycle which I dont think is correct in real world. I need to understand how I can accurately obtain traffic on L1-L2 bus as if my system is running on actual clock of a processor for example a PLL. Regards Aatmesh
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