What I have studied about x86(I have relatively small or what-so-ever no idea of x86-64) that pentium series used to have micro-programming decoding of instructions to risc like code before execution. Now for O3 execution these codes(generated after decoding of one instruction) must be executed in sequential manner to maintain precise exception between them as it corresponds to one instruction of original code or there must be some logic to sort this out. So can you tell me any source where I can read information regarding this. And also I inquired about documentation of m5sim. Please I would like to very much help in this because I want to understand working of these processors. I am fine till 80386, but as the cache and out of order came I am lost....
>There are differences, but they're mostly in the details. We tend towards the >AMD version of the architecture because those were the manuals I worked from >when writing the majority of the x86 >code, but our simulation isn't exact >enough that the relatively obscure differences matter. We don't model any >particular implementation's microarchitecture. > >Gabe > >On 12/1/2010 11:27 PM, Sudhanshu(Duke) wrote: >> Can anyone tell me which x86_64 machine is being considered here. I am >> new to simulators, so correct me if I am wrong. I think all x86-64 >> machines like Intel Core 2 and Amd 64 will have different >> implementation causing a bit different simulation. And I wanted to >> know if there is documentation for the code or an ongoing discussion >> for the same(I am interested in x86-64, cause I have only that >> machines in our college). I would highly appreciate if you could >> direct me to the correct direction. >> >> >> >>-- >>Sudhanshu([email protected], [email protected] & >>[email protected]) >> Sudhanshu([email protected], [email protected] & [email protected]) _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
