Hi Gabe, Thank you for the reply. May I know what is the best known method to trace the address range of the device ??
Or might it be there any possible that the compiled linux kernel for the alpha architecture does not have the driver on that ?? If i were to create the new linux kernel for the alpha architecture for the M5 simulator to run in a full system simulation mode with my GPU plugin on that, i just replace the existing vmlinux file that provided by M5 simulator ? Am I right ? regards wj On Mon, Dec 6, 2010 at 3:29 PM, <[email protected]> wrote: > Send m5-users mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of m5-users digest..." > > > Today's Topics: > > 1. Re: cc1plus: warnings being treated as errors (Gabe Black) > 2. Re: Graphic Device Plugin into M5 simulator (Gabe Black) > 3. Re: Out of order support in PowerPC (Timothy M Jones) > 4. error in running spec2006 in Alpha SE mode (Gdansk Amir) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Sun, 05 Dec 2010 02:13:34 -0800 > From: Gabe Black <[email protected]> > To: M5 users mailing list <[email protected]> > Subject: Re: [m5-users] cc1plus: warnings being treated as errors > Message-ID: <[email protected]> > Content-Type: text/plain; charset=ISO-8859-1 > > I was thinking more like defining a base Event class with common > elements and then base classes that do what the select statements would > have specialized them to do. Then the enums become unnecessary and the > problem goes away. I might give that a try one of these days, time > permitting. > > Gabe > > Korey Sewell wrote: > > Thanks for that update Gabe. > > > > Interesting that 4.5.1 I guess is doing some types of bounds checking > > on enums and since there is one enum list (RespoolEventType) that > > starts its enumeration from the end of another enum list > > (CPUEventType) then it kind of cries "not working!" at that point. > > > > The fix is probably just to merge the two lists and then to > > annotate/comment that at a certain point they are more resource pool > > specific then CPU specific. > > > > On Sun, Dec 5, 2010 at 2:53 AM, Gabriel Michael Black > > <[email protected]> wrote: > > > >> The attached patch should fix it. In my opinion this fixes a symptom and > the > >> way events are organized in InOrder should probably be revisited to make > it > >> unnecessary, but it should at least get things building for you. > >> > >> Gabe > >> > >> Quoting "Sudhanshu(Duke)" <[email protected]>: > >> > >> > >>> I am using gcc 4.5.1 on fedora 14-i686 > >>> > >>> > >>> > ************************************************************************** > >>> > >>> > >>> What compiler are you using? It might be too old, in which case I'd > >>> suggest upgrading if possible, or it might be too new in which case we > >>> should try to make the code build correctly. > >>> > >>> Gabe > >>> > >>> Quoting "Sudhanshu(Duke)" <[email protected]>: > >>> > >>> > >>> Hi > >>> I was compiling m5sim and got following errors > >>> > >>> $ scons build/ALPHA_SE/m5.debug > >>> . > >>> . > >>> . > >>> [ CXX] ALPHA_SE/cpu/inorder/resource_pool.cc > >>> cc1plus: warnings being treated as errors > >>> build/ALPHA_SE/cpu/inorder/resource_pool.cc: In member function > 'void > >>> ResourcePool::scheduleEvent(InOrderCPU::CPUEventType, > >>> ResourcePool::DynInstPtr, int, int, ThreadID)': > >>> build/ALPHA_SE/cpu/inorder/resource_pool.cc:326:7: error: case value > >>> '10' not in enumerated type 'InOrderCPU::CPUEventType' > >>> build/ALPHA_SE/cpu/inorder/resource_pool.cc:358:7: error: case value > >>> '11' not in enumerated type 'InOrderCPU::CPUEventType' > >>> build/ALPHA_SE/cpu/inorder/resource_pool.cc: In member function > >>> 'virtual void ResourcePool::ResPoolEvent::process()': > >>> build/ALPHA_SE/cpu/inorder/resource_pool.cc:525:7: error: case value > >>> '10' not in enumerated type 'InOrderCPU::CPUEventType' > >>> build/ALPHA_SE/cpu/inorder/resource_pool.cc:533:7: error: case value > >>> '11' not in enumerated type 'InOrderCPU::CPUEventType' > >>> scons: *** [build/ALPHA_SE/cpu/inorder/resource_pool.do] Error 1 > >>> scons: building terminated because of errors. > >>> > >>> please suggest a way to toggle Werror.... I don-t know from where to > >>> toggle it.... I recently downloaded a copy of m5 using mercurial(m5 > >>> and not m5-stable). Please advise what to do... > >>> > >>> -- > >>> Sudhanshu([email protected], [email protected] & > >>> [email protected]) > >>> _______________________________________________ > >>> m5-users mailing list > >>> [email protected] > >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > >>> > >>> > >>> _______________________________________________ > >>> m5-users mailing list > >>> [email protected] > >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > >>> > >>> > >>> -- > >>> Sudhanshu([email protected], [email protected] & > >>> [email protected]) > >>> _______________________________________________ > >>> m5-users mailing list > >>> [email protected] > >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > >>> > >>> > >> > >> _______________________________________________ > >> m5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > >> > >> > > > > > > > > > > > > ------------------------------ > > Message: 2 > Date: Sun, 05 Dec 2010 10:17:31 -0800 > From: Gabe Black <[email protected]> > To: M5 users mailing list <[email protected]> > Subject: Re: [m5-users] Graphic Device Plugin into M5 simulator > Message-ID: <[email protected]> > Content-Type: text/plain; charset=ISO-8859-1 > > It looks like your device is actually conflicting with itself and not > one of the other devices. You should double check how you (and/or base > classes) are specifying its address ranges and see if there's any > redundancy. It might help to make the bus print out what the conflicting > ranges actually are when it hits that panic to give you a better idea > where to look. > > Gabe > > Ong Wen Jian wrote: > > Hi Gabe,, > > > > I give you a more details about the error when I try to run the > > simulation , > > > > My configs/common/FSConfig.py code is here.... > > > > class BaseTsunami(Tsunami): > > ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) > > +GraphicDevice = TDFXGPU(pci_bus=0,pci_dev=2,pci_func=0) > > ide = IdeController(disks=[Parent.disk0, Parent.disk2], > > pci_func=0, pci_dev=0, pci_bus=0) > > > > ........other code....... > > > > self.tsunami = BaseTsunami() > > self.tsunami.attachIO(self.iobus) > > self.tsunami.ide.pio = self.iobus.port > > self.tsunami.ethernet.pio = self.iobus.port > > +self.tsunami.GraphicDevice.pio = self.iobus.port > > > > and the terminal when running in the full system simulation .. > > > > ==== m5 slave terminal: Terminal 0 ==== > > M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 > > Got Configuration 623 > > memsize 8000000 pages 4000 > > First free page after ROM 0xFFFFFC0000018000 > > HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt > > 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel > > 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 > > kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = > > 0xFFFFFC0000310000, numCPUs = 0x1 > > CPU Clock at 2000 MHz IntrClockFrequency=1024 > > Booting with 1 processor(s) > > KSP: 0x20043FE8 PTBR 0x20 > > Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 > > Memory cluster 0 [0 - 392] > > Memory cluster 1 [392 - 15992] > > Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 > > ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 > > unix_boot_mem ends at FFFFFC0000076000 > > k_argc = 0 > > jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn > > 1067) > > CallbackFixup 0 18000, t7=FFFFFC000070C000 > > Linux version 2.6.13 ([email protected] > > <mailto:[email protected]>) (gcc version 3.4.3) #1 SMP Sun Oct 8 > > 19:52:07 EDT 2006 > > Booting GENERIC on Tsunami variation DP264 using machine vector DP264 > > from SRM > > Major Options: SMP LEGACY_START VERBOSE_MCHECK > > Command line: root=/dev/hda1 console=ttyS0 > > memcluster 0, usage 1, start 0, end 392 > > memcluster 1, usage 0, start 392, end 16384 > > freeing pages 1069:16384 > > reserving pages 1069:1070 > > SMP: 1 CPUs probed -- cpu_present_mask = 1 > > Built 1 zonelists > > Kernel command line: root=/dev/hda1 console=ttyS0 > > PID hash table entries: 1024 (order: 10, 32768 bytes) > > Using epoch = 1900 > > Console: colour dummy device 80x25 > > Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) > > Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) > > Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, > > 983k data, 224k init) > > Mount-cache hash table entries: 512 > > SMP mode deactivated. > > Brought up 1 CPUs > > SMP: Total of 1 processors activated (4002.20 BogoMIPS). > > NET: Registered protocol family 16 > > EISA bus registered > > > > and on the host terminal > > > > **** REAL SIMULATION **** > > info: Entering event queue @ 0. Starting simulation... > > 4012053000: system.terminal: attach terminal 0 > > fatal: system.iobus has two ports with same range: > > system.tsunami.GraphicDevice-pioport > > system.tsunami.GraphicDevice-pioport > > @ cycle 10039875000 > > [recvStatusChange:build/ALPHA_FS/mem/bus.cc, line 529] > > > > Any guide to solve this problem ?? As I think I just left a step to > > achieve the graphic device plugin into M5 simulator to enabling GPU > > research related activity on M5. > > > > regards > > > > > > ONG WEN JIAN > > Student > > Department of Computer and Communication Systems Engineering, > > Faculty of Engineering, Universiti Putra Malaysia > > 43400 UPM Serdang, Selangor Darul Ehsan > > Tel : 014 - 930 2150 / 017 - 613 6231 > > ------------------------------------------------------------------------ > > > > _______________________________________________ > > m5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > ------------------------------ > > Message: 3 > Date: Sun, 05 Dec 2010 21:27:10 -0500 > From: Timothy M Jones <[email protected]> > To: Sameh Galal <[email protected]> > Cc: M5 users mailing list <[email protected]> > Subject: Re: [m5-users] Out of order support in PowerPC > Message-ID: <[email protected]> > Content-Type: text/plain; charset=ISO-8859-1; format=flowed > > Hi Sameh, > > Well, in terms of steering instructions to the correct functional units, > I think you should simply need to go through the decoder.isa file in > src/arch/power/isa and add the correct functional unit flag to the end > of each instruction. Slightly tedious but not too difficult. If you do > that, please post a patch onto the reviewboard so that we can get your > changes incorporated into the repository. > > I'm not totally sure I get what you mean about the dependent > accumulation instructions starting earlier. If you mean that you want > them to execute earlier, then you'll have to alter the O3PCU code to get > them marked as ready. I'm by no means an expert on O3, but I believe > you want to look at src/cpu/o3/iew_impl.hh as a starting point. > > Cheers > Tim > > On 04/12/2010 17:19, Sameh Galal wrote: > > Hi Tim, > > Thanks for your response. I am trying different designs of fused > > multiply add units in the powerpc architecture using SPEC 2000 floating > > point benchmarks. If you were planning to incorporate the functional > > units for the powerpc o3 design that will be great. Let me know if I can > > help with that. I am looking at possible designs that allow dependent > > accumulation instructions to start earlier. Do you have an idea which > > files will be best to look at to incorporate this modification. > > cheers, > > Sameh > > > > On Fri, Dec 3, 2010 at 7:15 AM, Timothy M Jones <[email protected] > > <mailto:[email protected]>> wrote: > > > > Hello, > > > > Just to add my clarifications. Firstly, Gabe is right that the > > classification of instructions was left out and I haven't got round > > to putting it in. I can do that, but not for a week or so. > > > > Secondly, Steve is also right, the out-of-order scheduling happens > > and instructions do get executed when they become ready. > > > > Power should work just fine with O3CPU and I've used it a fair bit > > without problems. All the SPEC 2000 integer benchmarks work on it, > > for example. However, if you do come across something that isn't > > working just let me know and I'll try to work out a fix with you. > > > > Cheers > > Tim > > > > > > On Thu, 02 Dec 2010 14:27:32 -0500, Steve Reinhardt > > <[email protected] <mailto:[email protected]>> wrote: > > > > No, that's not true... the out-of-order scheduling will happen > > regardless of > > functional unit assignment. I'm guessing that what happens is > > that all > > instructions get assigned to some default functional unit type > > (probably > > integer ALU), and I'm pretty sure the default O3 model has > > multiple integer > > ALUs, so I'm pretty confident you'd be getting out-of-order > > behavior. It's > > just not accurately reflecting the resource constraints of how > > instructions > > would map to different units. > > > > Steve > > > > On Thu, Dec 2, 2010 at 10:57 AM, Sameh Galal > > <[email protected] <mailto:[email protected]>> wrote: > > > > Thanks for the info. If that's true, then none of the > > instructions are > > assigned to any functional unit, i assume the machine just > > behaves like an > > in-order machine which is not what the O3 cpu model was > > built for .. > > > > Sameh > > > > > > On Wed, Dec 1, 2010 at 10:58 PM, Gabe Black > > <[email protected] <mailto:[email protected]>> > wrote: > > > > It should work functionally. It's quite possible > classifying > > instructions like that in Power was left for after > > things worked > > functionally and never revisited. This is almost > > certainly the case for > > some of the other ISAs. You can attempt to change the > > isa description > > yourself so that the right op class is used. Because the > > description is > > built in a custom language it can be tricky to figure > > out what's going > > on, but if Power is structured similar to Alpha then the > > op class > > setting code may be pretty easy to port if it isn't in > > there already. > > When you configure the functional unit in O3, don't > > change the file in > > src/ since those files only set the default value. > > You'll want to change > > the value in the CPU you're instantiating in a > > configuration script. > > That way you won't have to recompile M5 to try a new > value. > > > > Gabe > > > > Sameh Galal wrote: > > > Hi, > > > I have a quick question about how PowerPC out of > > order cpu model in SE > > > mode. Is the out of order model fully supported in > > PowerPC > > > > > > The reason I am asking, is that it is not clear to me > > how the > > > functional units of the PowerPC architecture are > > assigned their > > > latencies. I found that the file > > src\cpu\o3\FuncUnitConfig.py contains > > > the functional unit configuration and which > > instructions the units > > > handle. For example the FP_MultDiv unit handles the > > FloatMult > > > instructions among other instructions > > > > > > class FP_MultDiv(FUDesc): > > > opList = [ OpDesc(opClass='FloatMult', opLat=4), > > > OpDesc(opClass='FloatDiv', opLat=12, > > issueLat=12), > > > OpDesc(opClass='FloatSqrt', opLat=24, > > issueLat=24) ] > > > count = 2 > > > > > > However when I grep the source folder for FloatMult, > > I find that only > > > the alpha architecture instruction decoder assigns > > the Opclass types. > > > So how is the simulation of powerpc functional units > > done? > > > > > > [same...@cyclades-master m5]$ grep -r FloatMult ./src > > > ./src/arch/alpha/isa/decoder.isa: > > 0x02: muls({{ > > > Fc = Fa * Fb; }}, FloatMultOp); > > > ./src/arch/alpha/isa/decoder.isa: > > 0x02: muls({{ > > > Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); > > > ./src/arch/alpha/isa/decoder.isa: > > 0x22: mult({{ > > > Fc = Fa * Fb; }}, FloatMultOp); > > > ./src/cpu/FuncUnit.py: 'FloatCmp', 'FloatCvt', > > 'FloatMult', > > > 'FloatDiv', 'FloatSqrt', > > > ./src/cpu/o3/FuncUnitConfig.py: opList = [ > > > OpDesc(opClass='FloatMult', opLat=4), > > > ./src/cpu/op_class.hh:const OpClass FloatMultOp = > > Enums::FloatMult; > > > > > > Thanks for clarifying. > > > Sameh > > > > > > ------------------------------------------------------------------------ > > > > > > _______________________________________________ > > > m5-users mailing list > > > [email protected] <mailto:[email protected]> > > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > _______________________________________________ > > m5-users mailing list > > [email protected] <mailto:[email protected]> > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > > > > > _______________________________________________ > > m5-users mailing list > > [email protected] <mailto:[email protected]> > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > > > > > -- > > Timothy M. Jones > > http://homepages.inf.ed.ac.uk/tjones1 > > > > The University of Edinburgh is a charitable body, registered in > > Scotland, with registration number SC005336. > > > > > > _______________________________________________ > > m5-users mailing list > > [email protected] <mailto:[email protected]> > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > > > -- > Timothy M. Jones > http://homepages.inf.ed.ac.uk/tjones1 > > The University of Edinburgh is a charitable body, registered in > Scotland, with registration number SC005336. > > > > ------------------------------ > > Message: 4 > Date: Mon, 6 Dec 2010 15:32:10 +0800 > From: Gdansk Amir <[email protected]> > To: [email protected], [email protected] > Subject: [m5-users] error in running spec2006 in Alpha SE mode > Message-ID: > <[email protected]> > Content-Type: text/plain; charset="iso-8859-1" > > Hi, > When i use the command 'build/ALPHA_SE/m5.fast cmp.py -b bzip2' to run > the spec2006 benchmark in alpha_se mode, the terminate show full of this: > info: Increasing stack size by one page. then shows > 'fatal: Over max stack size for one thread > @ cycle 2219598500 > [checkAndAllocNextPage:build/ALPHA_SE/sim/process.cc, line 354] > Memory Usage: 155176 KBytes > For more information see: http://www.m5sim.org/fatal/18400806' > > and exit. I dont't know why? I follows the m5 web-site > http://m5sim.org/wiki/index.php/SPEC2006_benchmarks, > > the constant of Mybench.py is > #Mybench.py > import os > import optparse > import sys > > import m5 > from m5.objects import * > > > m5.util.addToPath('./configs') > m5.util.addToPath('./configs/common') > > #import Simulation > from Caches import * > import Simulation > > data_dir = "/m5/spec2006/benchspec/CPU2006/" > > #400.perlbench > perlbench = LiveProcess() > perlbench.executable = > > "/m5/spec2006/benchspec/CPU2006/400.perlbench/exe/perlbench_base.amd64-gcc4x" > #perlbench.executable = > > > /m5/spec2006/benchspec/CPU2006/400.perlbench/exe/+'400.perlbench_base.alpha-gcc' > perlbench.cmd = [perlbench.executable] + > ['-I/m5/spec2006/benchspec/CPU2006/400.perlbench/data/all/input/lib', ' > attrs.pl'] > perlbench.output = 'attrs.out' > > > #401.bzip2 > bzip2 = LiveProcess() > bzip2.executable = > '/m5/spec2006/benchspec/CPU2006/401.bzip2/exe/bzip2_base.amd64-gcc4x' > data='./data/all/input/input.program' > bzip2.cmd = [bzip2.executable] + [data, '1'] > bzip2.output = './data/all/input/input.program.out' > > > when i run the 400 benchmark, it is ok. I have copy the data directory of > 401 in the work directory. > Could you tell me why?? > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/m5-users/attachments/20101206/4c0e3304/attachment.html > > > > ------------------------------ > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > End of m5-users Digest, Vol 53, Issue 9 > *************************************** > -- ONG WEN JIAN Student Department of Computer and Communication Systems Engineering, Faculty of Engineering, Universiti Putra Malaysia 43400 UPM Serdang, Selangor Darul Ehsan Tel : 014 - 930 2150 / 017 - 613 6231
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