I assume your request it letting L2 cache refill the data, but L1 cache bypass
the data.
Look at the handleFill code in cache_impl.hh.
blk = allocateBlock(addr, writeback);
if(blk == NULL){
…
If the (blk==NULL), then the data is bypassed by this cache (I think this is
what you mean “not write”).
You can achieve this by slight change allocateBlock, letting it always return
NULL when using a new replacement policy (you also need to add a replacement
policy in mem/cache/tags directory).
发件人: [email protected] [mailto:[email protected]] 代表 Keitarou
Oka
发送时间: 2010年12月7日星期二 14:26
收件人: M5 users mailing list
主题: Re: [m5-users] 答复: How to get write value in L2cahce
I'm sorry that I could not reply you sooner.
Second question is how can I get write value to block only in L2cache.
I think HandleFill() include write to block in L1 and L2 cache.
I add DPRINTF to HandleFill() in cache_imple.hh to get write value by
HandleFill().
DPRINTF(Cache,"data_by_HandlFill():%x\n",*(pkt->getPtr<uint8_t>()));
result show that handleFill write value in L1(icache) and L2cache.
result is following
command line: ../build/ALPHA_SE/m5.opt --trace-flags=Cache -d output
../configs/splash2/run.py -n 8 -b Cholesky --l2shared --l1size=32kB --l1assoc=2
--l1latency=1 --l2size=1024kB --l2assoc=8 --l2latency=12
Global frequency set at 1000000000000 ticks per second
0: system.cpu6.icache: ReadReq 1e840 miss
500: system.l2cache: ReadReq 1e840 miss
156500: system.l2cache: Handling response to 1e840
156500: system.l2cache: Block for addr 1e840 being updated in Cache
156500: system.l2cache: Block addr 1e840 moving from state 0 to 7
156500: system.l2cache: data_by_handleFill:f0
168000: system.cpu6.icache: Handling response to 1e840
168000: system.cpu6.icache: Block for addr 1e840 being updated in Cache
168000: system.cpu6.icache: Block addr 1e840 moving from state 0 to 5
168000: system.cpu6.icache: data_by_handleFill:f0
169500: system.cpu6.icache: ReadReq 1e844 hit
170000: system.cpu6.icache: ReadReq 1e844 hit
170500: system.cpu6.dcache: WriteReq e1ff8 miss
171000: system.l2cache: ReadExReq e1fc0 miss
327000: system.l2cache: Handling response to e1fc0
327000: system.l2cache: Block for addr e1fc0 being updated in Cache
327000: system.l2cache: Block addr e1fc0 moving from state 0 to 7
327000: system.l2cache: data_by_handle Fill:0
(2010/12/03 21:34), zhanglunkai wrote:
For the first question,
Access()'s memcpy is for WriteBXK data, these are data evicted from higher
level caches.
HandleFill()'s memcpy is for ReadReq(or ReadExReq) data, these data are from
lower level caches (or memory).
For the second question,
I don't quite understand what you mean by "write data to cache" ...
conventional caches are not changed the content of its storage. It can only
store these data.
-----邮件原件-----
发件人: [email protected] [mailto:[email protected]] 代表 Oka
Keitarou
发送时间: 2010年12月3日星期五 20:10
收件人: [email protected]
主题: Re: [m5-users] How to get write block data
Thank you for reply.
I looked at access() and handleFill() in cache_impl.hh,and I had two
quetions.
Fisrt,I didn't understand difference between access() and handleFill().
Shoud I have to insert "DPRINTF" both of access() and handleFill()?
Second,how can I pick out write data to only L2cache?
I think these functions include write to both of L1cache and L2cache.
Thanks
oka
---------------------------------------------------------------------
zhanglunkai
Thu, 02 Dec 2010 23:50:35 -0800
Look at access() and handleFill() functions in cache_impl.hh.
Both of these two functions use memcpy to write data to L2 cache.
-----邮件原件-----
发件人: [email protected] [mailto:[email protected]] 代表
Oka Keitarou
发送时间: 2010年12月3日星期五 12:03
收件人: [email protected]
主题: [m5-users] How to get write block data to L2 cache
Hi,
I'd like to get the information of write block data to L2 cache.
I found in srm/mem/cache/cache_impl.hh that "pkt->getPtr<uint8_t>" is
pointer to data.
so I want to add like following code.
DPRINTF(Cache,"L2blkdata%x",*(pkt->getPtr<uint8_t>()))
However I can't find where pkt is written to L2 cache.
Could you tell me how can I get block data to L2 cache?
thanks
oka
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