Hi, I am adding my prefetching idea to the m5 simulator. But several memory intensive benchmarks cannot run correctly (some of these benchmarks' statistics are obvious wrong, and others will end abnormally).
These phenomenon happened when I run benchmarks in detail mode for 250-million instructions (with 5-billion instructions in atomic mode). So it so hard to tell where does the things go wrong. I am looking into the cache_impl.hh and mshr*, and trying to figure out where is the problem. Some of the mshr's code I cannot fully understand, here is the question: I find that m5 only issue prefetching when mshr is empty, using allocteMissBuffer() function. What is the relationship between mshr and MissBuffer&WriteBuffer? When m5 issues a prefetch, does mshr record this prefetch?
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