initially by using findBlock it gets the block and then invalidated all the blocks, my point is when a cpu requests, it will check the tag and valid bits for hit else its a miss. yeah it's not possible in set associative caches but what about direct mapped?
On Fri, Feb 4, 2011 at 8:49 PM, Nilay Vaish <[email protected]> wrote: > On Fri, 4 Feb 2011, biswabandan panda wrote: > > hey thanks,that i know but the problem is how to find the block within >> the >> set, because all the codes are written in such a way that it takes care of >> hits only >> >> On Fri, Feb 4, 2011 at 8:41 PM, Nilay Vaish <[email protected]> wrote: >> >> On Fri, 4 Feb 2011, biswabandan panda wrote: >>> >>> miss to a particular block in a particular set >>> >>>> >>>> On Fri, Feb 4, 2011 at 8:34 PM, Nilay Vaish <[email protected]> wrote: >>>> >>>> On Fri, 4 Feb 2011, biswabandan panda wrote: >>>> >>>>> >>>>> Hi all, >>>>> >>>>> i want to generate block address and set nos for the misses >>>>>> also >>>>>> in line no 326 to 328 cache_impl.hh. i have done it for hits for >>>>>> misses >>>>>> , >>>>>> i am facing problems because the blocks findBlk and findBlock returns >>>>>> only >>>>>> the hit blocks and after that there is use of (blk != NULL) which >>>>>> checks >>>>>> it >>>>>> again. Any idea how i can generate traces of blocka ddress and set >>>>>> numbers >>>>>> for misses also. >>>>>> >>>>>> i have done in this way for hits >>>>>> : >>>>>> DPRINTF(Cache, "%s %s %d %x %s\n", pkt->cmdString(), >>>>>> pkt->req->isInstFetch() ? "(ifetch)" : "", >>>>>> blk->set, tags->regenerateBlkAddr(blk->tag,blk->set),blk ? >>>>>> "hit" >>>>>> : "miss"); >>>>>> >>>>>> >>>>>> >>>>>> How can a miss have a set number? pkt->getAddr() should yield the >>>>>> >>>>> address >>>>> that was being accessed. >>>>> >>>>> -- >>>>> >>>>> >>>> tags->extractSet(address) should give you the set. >>> >>> >>> > Again, how can a cache miss have a block with in a set? > > > -- > Nilay > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- *thanks®ards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ <http://www.cse.iitm.ac.in/%7Ebiswa/>
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