Thanks a lot for your help!
I think I must missed something since I looked at baseCPU.py, the
addTwoLevelCacheHierarchy seems to just add L1 and L2, but not L3. Could you
elaborate more?
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)
self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c
self.l2cache.cpu_side = self.toL2Bus.port
self._mem_ports = ['l2cache.mem_side']
Thanks!
-Sheng
On Fri, Feb 4, 2011 at 11:48 AM, biswabandan panda <[email protected]>wrote:
> no if you want to use l3 it will create 2 levels at that time else u need
> not to
>
>
> On Fri, Feb 4, 2011 at 10:16 PM, Sheng Li <[email protected]> wrote:
>
>> Thanks!
>>
>> Why would I need to addTwoLevelCacheHierarchy? I looked at the Cache.py,
>> when connect the L2 cache, we only need to do "system.l2 =
>> L2Cache(size='2MB') ...."
>>
>> Thanks
>> -Sheng
>>
>>
>> On Fri, Feb 4, 2011 at 11:35 AM, biswabandan panda
>> <[email protected]>wrote:
>>
>>> yeah u can implement of your own like this:
>>>
>>> class L3(BaseCache):
>>> size = "8MB"
>>> block_size = 64
>>> latency = "24ns"
>>> mshrs = 8
>>> tgts_per_mshr = 4
>>> write_buffers = 8
>>> assoc = 16
>>>
>>> and use this function:. addTwoLevelCacheHierarchy and add cpuside ports
>>> and memory side ports for l3 cache
>>>
>>>
>>>
>>>
>>>
>>>
>>> On Fri, Feb 4, 2011 at 9:55 PM, Sheng Li <[email protected]> wrote:
>>>
>>>> Hi Guys,
>>>>
>>>> I am a newbie to M5. When running M5, I coded some python scripts and
>>>> used the default python files in ./config/ as the base. However, I realized
>>>> that some options in the Option.py were not implemented. For example, the
>>>> l3cache related options are in the Option.py file but not implemented
>>>> anywhere. Did I miss something? I can implement those are missing and just
>>>> want to make sure I am not missing some thing obvious.
>>>>
>>>> Thanks!
>>>> -Sheng Li
>>>>
>>>>
>>>>
>>>> _______________________________________________
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>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>>>
>>>
>>>
>>>
>>> --
>>>
>>> *thanks®ards
>>> *
>>> *BISWABANDAN PANDA*
>>> *M.S.(RESEARCH SCHOLAR)*
>>> *RISE LAB*
>>> *IIT MADRAS*
>>>
>>> http://www.cse.iitm.ac.in/~biswa/ <http://www.cse.iitm.ac.in/%7Ebiswa/>
>>>
>>>
>>>
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>>
>>
>> _______________________________________________
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>
>
>
> --
>
> *thanks®ards
> *
> *BISWABANDAN PANDA*
> *M.S.(RESEARCH SCHOLAR)*
> *RISE LAB*
> *IIT MADRAS*
>
> http://www.cse.iitm.ac.in/~biswa/ <http://www.cse.iitm.ac.in/%7Ebiswa/>
>
>
>
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> m5-users mailing list
> [email protected]
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>
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