And what are the exact stats names that you're comparing? With an o3 cpu some stats that count instructions don't care if the instruction was useful (not squashed). What architecture as well? I'm not sure how good of a job we do identifying nops and such and not counting them in commit when they're sent down the pipe along with a fault or similar.
Ali On Tue, 8 Feb 2011 16:59:41 -0500, Korey Sewell wrote: Which CPU model(s) are you using? what mode (FS or SE)? On Tue, Feb 8, 2011 at 4:25 PM, Sheng Li wrote: Hi Guys, I am simulating SPECCPU2006 and changing MSHR setup for each simulation. I was surprised to see that for the same benchmark, if I just change the number of MSHRs I will get different simulated instructions, cache accesses, etc. I can expect that the timing (cycles) and some other stats may change. But how come the instruction count, cache accesses, etc changed too? The benchmarks finished properly with valid output. Did I missed something? Thanks -Sheng _______________________________________________ m5-users mailing list m5-users@m5sim.org [2] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users [3] -- - Korey Links: ------ [1] mailto:sheng....@gmail.com [2] mailto:m5-users@m5sim.org [3] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
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