thanks, Ali but I didn't see others memory accesses from CPU1, CPU2 and CPU3. I always saw CPU0's caches request memory access. Is it expected, too?
Dave On Wed, Feb 16, 2011 at 6:57 AM, Ali Saidi <[email protected]> wrote: > Things like writing a value into a user level data structure during syscall > emulation are done with functional accesses to the memory system. It's > expected. > > Take a look at the wiki page on the type of memory system requests. > > Ali > > > On Feb 16, 2011, at 3:43 AM, Dave wrote: > > Hi all, > When I watched the trace of the simpleCPU's cache timing model, I found > something is strange. > the command is as following, > *build/ALPHA_SE/m5.debug --trace-flags=SyscallVerbose,Bus,Cache > configs/splash2/run.py -t -n4 -bFFT* > > 17365000: system.membus: The bus is now occupied from tick 17365000 to > 17367000 > 17377000: system.toL2bus: recvTiming: src 0 dst 1 ReadResp 0x75480 > 17377000: system.cpu0.icache: Handling response to 75480 > 17377000: system.cpu0.icache: Block for addr 75480 being updated in Cache > 17377000: system.cpu0.icache: replacement: replacing 6d480 with 75480: > clean > 17377000: system.cpu0.icache: Block addr 75480 moving from state 0 to 7 > 17377000: system.toL2bus: The bus is now occupied from tick 17377000 to > 17379000 > 17380000: system.cpu0.icache: ReadReq (ifetch) 75494 hit > 17381000: system.cpu0: syscall uname called w/arguments > 5368717312,0,5368717313,4831387392 > 17381000: system.cpu0.dcache: functional WriteReq c5f00 valid > 17381000: system.toL2bus: recvFunctional: packet src 2 dest -1 addr 0xc5f00 > cmd WriteReq > 17381000: system.cpu0.icache: functional WriteReq c5f00 > 17381000: system.cpu1.icache: functional WriteReq c5f00 > <-------------------------------------------------------cpu1, cpu2 and cpu3 > are only accessed by functional access > 17381000: system.cpu1.dcache: functional WriteReq c5f00 > 17381000: system.cpu2.icache: functional WriteReq c5f00 > 17381000: system.cpu2.dcache: functional WriteReq c5f00 > 17381000: system.cpu3.icache: functional WriteReq c5f00 > 17381000: system.cpu3.dcache: functional WriteReq c5f00 > > The behavior of CPU0 looks fine in timing, but cpu1, cpu2, cpu3 only access > memory when syscall (@17381000) and through the functional access. > Does anyone know the reason?! > > thanks, > Dave > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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