Without having actually looked at the code in reference to this, if
the data was junk, either normal, non-speculative execution would have
also read the unmodified junk, or the memory at those addresses would
have been modified and the cached data would have been overwritten.
There's an important difference between uninitialized data and corrupt
data, namely whether the data is arbitrary or wrong. If it was
arbitrary but consistent, O3 and the timing CPU should get the same
arbitrary answer. If it was corrupted in the cache then their
different caching behavior could cause different pieces of data to be
corrupted and make them behave differently. I don't think things are
breaking as you described. It's quite possible, though, that there's a
bug in the O3 CPU that isn't hit under normal circumstances that
you're running into.
You mentioned large prefetch depth and issue width. You might look
into whether only one of those still makes O3 hit the bug. That might
narrow down your search. You can also use the tracediff utility to
compare execution between the timing CPU and O3 and see where things
diverge. There's more information about tracediff on the website.
Gabe
Quoting "Bryan S. Kim" <[email protected]>:
Hello,
We've been investigating very large prefetch depths in system
emulation mode and came across an interesting phenomenon. Under a
subset of benchmarks and configurations, segmentation faults (panic:
tried to access unmapped address) are observed.
Previous posts on "tried to access unmapped address" suggest that it
may have been caused by cache data corruption, and we are wondering
if the following situation is plausible.
O3CPU (detailed sim) speculatively accesses a piece of data which in
turn prefetches a bunch of data ahead of the CPU. Because these data
are so much ahead of the execution path, the data values are
uninitialized and hence corrupt data. We are suspecting this because
it works fine with timing simulation.
Has anyone encountered this situation with O3CPU with large issue
width and large prefetch depths? Thanks!
-Bryan
_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users