I want the read and write latencies for caches to be different. Is it ok, to change the latency numbers in cache_impl.hh when there is a write (by checking pkt->isWrite()), or do I need to take care of something else?
---- Adwait >
_______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
