Hi Korey, I see that in the inorder model, requests for resources in the resource pool are kind of tied to an instruction(DynInstPtr). Like, ResReqPtr Resource::request(DynInstPtr inst); Even, the wiki page says that Resources consists of any CPU object that an instruction wants to access.
But I want to be able to make use of some predefined resources out of the resource pool to be used in some stages of the "pipelined" unit that I am planning to put together. As I said before, this "pipelined" unit is not tied to any instruction and will only do some monitoring and processing work, aside the main instruction pipeline. How could I issue requests for resources in any stage of this separate "pipeline" in this case? Will creating some equivalent to the dummy instructions to be fed into this pipelined unit work? Thanks, Reena On Sun, May 1, 2011 at 1:23 AM, reena panda <[email protected]> wrote: > > Thanks a lot for replying Korey. > > > On Sat, Apr 30, 2011 at 10:33 AM, Korey Sewell <[email protected]> wrote: > >> oh fudge...make sure you send emails to the list so everyone can benefit >> from conversation. >> >> reposting. >> >> >> On Sat, Apr 30, 2011 at 11:13 AM, reena panda <[email protected]>wrote: >> >>> Hi, >>> >>> I think I was not clear with the questions in my previous emails. All I >>> basically want to achieve is to have a parallel helper unit side by side the >>> main pipeline. This helper unit would not act upon instructions directly, >>> but would rather continuously monitor certain activity in the actual >>> pipeline and do its processing. But as I said, the work it performs would >>> take more cycles and so, I would like to split it into more stages which do >>> some distinct parts of the work. So, as you had previously suggested, I >>> definitely need to apply certain changes to the tick functionality. But I >>> was wondering if I could take pointers from the any of the existing >>> structures in the m5 inorder model and make changes to it because I think I >>> also would need structures to enable communication between the >>> sub-computation stages in the helper unit. Or is there any other way I can >>> achieve this? I am not quite sure if I could do this. Can you give me some >>> pointers? >>> >>> Just an aside, what are dummy instructions used for in the inorder >>> pipeline? >>> Thanks, >>> Reena >>> >>> >>> >>> On Fri, Apr 29, 2011 at 10:17 AM, reena panda <[email protected]>wrote: >>> >>>> Hi Korey, >>>> >>>> Thanks for replying. Yeah, I was also slightly skeptical to use the term >>>> "pipeline", but I could not come up with some thing appropriate :). >>>> >>>> Yes, you are correct in some sense that I want to be able to monitor the >>>> activity in the actual instruction pipeline and do some post-processing on >>>> what I monitor. So, this will be kind of a parallel helper unit, which >>>> would >>>> monitor certain events in the instruction pipeline (but would not be tied >>>> to >>>> any stage/instruction itself) and should be able to do some independent >>>> processing on it. But this post-processing work cannot be done in a single >>>> cycle and so, I want it to be split into stages of work that can talk to >>>> each other (that's why termed it a pipeline). Finally, in my case, the >>>> helper unit's work will be used to aid in prefetching and hence I want it >>>> to >>>> be timed properly. Do I make sense? >>>> >>>> Also, I would want to use certain resources from the resource pool(if >>>> there are free slots) during these post processing steps in the helper >>>> unit. >>>> But I was unsure how could I do that given that current resources can be >>>> only used/issued by instructions. >>>> >>>> Thanks, >>>> Reena >>>> >>>> >>>> On Fri, Apr 29, 2011 at 8:18 AM, Korey Sewell <[email protected]>wrote: >>>> >>>>> "What I mean is that this parallel pipeline might be able to watch over >>>>> the main instruction pipeline, but would do not instruction processing. " >>>>> How is it a pipeline if no instructions are going through it? >>>>> >>>>> Sounds like you want to attach some type of monitoring unit. If so, you >>>>> can probably add something to the cpu->tick() function which calls tick() >>>>> on >>>>> all the pipeline stages. You can either do some monitoring before each >>>>> pipeline stage is run or at the end of each cycle do some monitoring on >>>>> the >>>>> whole pipeline. >>>>> >>>>> >>>>> -- >>>>> - Korey >>>>> >>>>> _______________________________________________ >>>>> m5-users mailing list >>>>> [email protected] >>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>>>> >>>> >>>> >>> >> >> >> -- >> - Korey >> > >
_______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
