I m trying to invalidate some block in L2. If the blocks are dirty, I m writing it back using allocateWriteBuffer functionality. If they are not dirty and are valid I m invalidating them directly. It seems coherence is broken somewhere. Any help on this appreciated. This may be the reason for halt. ---- Adwait
On Thu, May 12, 2011 at 12:30 PM, Adwait Jog <[email protected]> wrote: > Thanks Nilay. I tried using warn instead of panic, but its still > crashing saying all cpus are halted. > > I have checkpointed till beginning of ROI, warming up for 100M > instructions in ROI and then switching to > detailed mode (using -s -W 100000000 option). There are some issues it seems > during warming up of PARSEC in ROI. I m using simsmall and running > full ROI. (in FS mode) > > I will try to figure out where the halt is called from. Any > ideas/suggestions to fix is appreciated. > > ---- Adwait > > > > On Thu, May 12, 2011 at 11:31 AM, Adwait Jog <[email protected]> wrote: >> Is it a good idea to put warn instead of panic at line 385. Will it >> effect the correctness or lead into other issues?. >> Any help is appreciated. >> ---- Adwait >> >> >> >> On Thu, May 12, 2011 at 1:06 AM, Adwait Jog <[email protected]> wrote: >>> Hi All: >>> >>> Can anyone please tell what could be the reason for the following panic. >>> I m using PARSEC benchmarks on M5 in FS mode. >>> >>> warn: Prefetch instrutions is Alpha do not do anything >>> For more information see: http://www.m5sim.org/warn/3e0eccba >>> panic: Halt not implemented! >>> @ cycle 2290180896000 >>> [halt:build/ALPHA_FS/cpu/o3/cpu.hh, line 385] >>> >>> >>> ---- Adwait >>> >> > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
