Hi M5, I'm practicing some little changes on M5 cache architecture and replacement policy. In file M5/src/mem/cache/cache.hh bool access(PacketPtr pkt, BlkType *&blk, int &lat, PacketList &writebacks); Is the source (src) of pkt means the CPUid, which send this pkt through bus to L2?
I want to simulate 4 CPUs on each runs one single-thread app, e.g. app0 on CPU0, app1 on CPU1, app2 on CPU2, and app3 on CPU3. And there are two different L2 settings: 1. simple 16-way-associative L2 cache, shared by 4 CPUs. 2. 4-way-associative L2 cache for each CPU. My methodology is that creat 16-way-associative cache, and then accesses from CPU0 can only use way0-3, CPU1 can only use way4-7 and so on. I found that only Addr gets into tag, so I need to get CPUid for my idea. Thank you. Mark Chen _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
