That's the whole bus bandwidth. It could very well limit performance depending on its properties and how it's integrated into the system.
Gabe On 06/08/11 08:56, Dawei Wang wrote: > Hello, everyone > > Now I am simulating M5 with more than 16 cores. Each core has its > private L1 I&D cache, and every L1 cache share one big L2 cache. > My question is when the number of cores become larger and larger, will > the tol2bus become the whole system bottleneck? > > I have seen the bus.hh and Bus.py. I know the default configuration is > 1GHz and 64 Byte width. But I didn't see any bus arbitration. So the > 64GB/s is whole bus bandwidth, or any peer-to-peer link bandwidth. > Therefore, I wonder whether the tol2bus will become performance limiter? > > > Many thanks in advance. > Dawei > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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