Thanks Ali. It works when I manually update config.ini to change the block size. But, its not working when I use "cacheline_size" parameter from command line.
On Thu, Jun 9, 2011 at 2:16 AM, Ali Saidi <[email protected]> wrote: > You need to set all the cache line sizes to the same thing. Check > config.ini you must have missed one of them. > > Ali > > On Jun 7, 2011, at 10:39 AM, Abhishek Rawat wrote: > > > Hi everyone, > > > > I am running O3 cores in ALPHA FS. I am trying to change the cache line > size of caches. But I keep getting following error : > > > > fatal: port A size 64, port B size 128 > > Busses don't have the same block size... Not supported. > > @ cycle 0 > > [init:build/ALPHA_FS/mem/bridge.cc, line 99] > > > > I figured that the bridge implementation expects the block sizes to be > same. And so I have made following changes: > > -- system.tol2bus = Bus(block_size=options.cacheline_size) in > CacheConfig.py > > -- self.iobus = Bus(bus_id=0, block_size=options.cacheline_size) in > FSConfig.py > > -- self.membus = MemBus(bus_id=1, block_size=options.cacheline_size) in > FSConfig.py > > > > But, I am still getting the same error. Am I missing something ? > > > > > > Thanks, > > -Abhishek > > > > Graduate Student > > Computer Science > > University of Virginia > > > > > --------------------------------------------------------------------------------------------------------------------- > > simplicity is the ultimate sophistication > > -Leonardo da Vinci > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- -Abhishek Graduate Student Computer Science University of Virginia --------------------------------------------------------------------------------------------------------------------- simplicity is the ultimate sophistication -Leonardo da Vinci
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