commit: ec6fea76e9946ac1e928021e2d774e70195831c2 Author: Sam James <sam <AT> gentoo <DOT> org> AuthorDate: Sat Jul 19 12:02:50 2025 +0000 Commit: Sam James <sam <AT> gentoo <DOT> org> CommitDate: Sat Jul 19 12:03:50 2025 +0000 URL: https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=ec6fea76
profiles/features/llvm: add transitory p.use.force for LLVM_TARGETS Gradually unforce targets for LLVM profiles as clang temporarily breaking isn't okay there (as it can't then build itself). This means the fix for bug #767700 is delayed on these profiles until old LLVMs age out. This pulls in the entries from b7a956ed5e89120b44bc650839ba1786c163941e but adjusted. Bug: https://bugs.gentoo.org/767700 Signed-off-by: Sam James <sam <AT> gentoo.org> profiles/features/llvm/package.use.force | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/profiles/features/llvm/package.use.force b/profiles/features/llvm/package.use.force index 045327290ad8..e6ebda8e75bb 100644 --- a/profiles/features/llvm/package.use.force +++ b/profiles/features/llvm/package.use.force @@ -1,6 +1,100 @@ # Copyright 2023-2025 Gentoo Authors # Distributed under the terms of the GNU General Public License v2 +# Sam James <[email protected]> (2025-07-19) +# Gradually unforce targets for LLVM profiles as clang temporarily +# breaking isn't okay there (as it can't then build itself). This means +# the fix for bug #767700 is delayed on these profiles until old LLVMs +# age out. +<llvm-core/clang-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/clang-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/clang-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/clang-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/clang-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/clang-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/clang-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/clang-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/clang-21 llvm_targets_VE +<llvm-core/clang-21 llvm_targets_LoongArch +<llvm-core/clang-21 llvm_targets_SPIRV +<llvm-core/llvm-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/llvm-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/llvm-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/llvm-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/llvm-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/llvm-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/llvm-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/llvm-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/llvm-21 llvm_targets_VE +<llvm-core/llvm-21 llvm_targets_LoongArch +<llvm-core/llvm-21 llvm_targets_SPIRV +<llvm-core/lld-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/lld-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/lld-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/lld-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/lld-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/lld-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/lld-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/lld-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/lld-21 llvm_targets_VE +<llvm-core/lld-21 llvm_targets_LoongArch +<llvm-core/lld-21 llvm_targets_SPIRV +<llvm-core/lld-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/lld-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/lld-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/lld-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/lld-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/lld-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/lld-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/lld-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/lld-21 llvm_targets_VE +<llvm-core/lld-21 llvm_targets_LoongArch +<llvm-core/lld-21 llvm_targets_SPIRV +<llvm-core/flang-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/flang-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/flang-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/flang-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/flang-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/flang-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/flang-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/flang-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/flang-21 llvm_targets_VE +<llvm-core/flang-21 llvm_targets_LoongArch +<llvm-core/flang-21 llvm_targets_SPIRV +<llvm-core/lldb-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/lldb-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/lldb-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/lldb-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/lldb-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/lldb-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/lldb-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/lldb-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/lldb-21 llvm_targets_VE +<llvm-core/lldb-21 llvm_targets_LoongArch +<llvm-core/lldb-21 llvm_targets_SPIRV +<llvm-core/lldb-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/lldb-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/lldb-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/lldb-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/lldb-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/lldb-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/lldb-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/lldb-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/lldb-21 llvm_targets_VE +<llvm-core/lldb-21 llvm_targets_LoongArch +<llvm-core/lldb-21 llvm_targets_SPIRV +<llvm-core/lldb-21 llvm_targets_AArch64 llvm_targets_AMDGPU +<llvm-core/lldb-21 llvm_targets_ARM llvm_targets_AVR llvm_targets_BPF +<llvm-core/lldb-21 llvm_targets_Hexagon llvm_targets_Lanai +<llvm-core/lldb-21 llvm_targets_MSP430 llvm_targets_Mips +<llvm-core/lldb-21 llvm_targets_NVPTX llvm_targets_PowerPC +<llvm-core/lldb-21 llvm_targets_RISCV llvm_targets_Sparc +<llvm-core/lldb-21 llvm_targets_SystemZ llvm_targets_WebAssembly +<llvm-core/lldb-21 llvm_targets_X86 llvm_targets_XCore +<llvm-core/lldb-21 llvm_targets_VE +<llvm-core/lldb-21 llvm_targets_LoongArch +<llvm-core/lldb-21 llvm_targets_SPIRV + # Sam James <[email protected]> (2023-03-03) # Force the toolchain environment we expect on the LLVM profiles. # default-libcxx in particular changes ABI so can't be toggled at-will, and other
