commit: 0c39134cf26f4454e2ab37b2e940af0800e03541
Author: Huang Rui <vowstar <AT> gmail <DOT> com>
AuthorDate: Sat Dec 6 04:19:30 2025 +0000
Commit: Rui Huang <vowstar <AT> gmail <DOT> com>
CommitDate: Sat Dec 6 04:19:30 2025 +0000
URL: https://gitweb.gentoo.org/repo/proj/guru.git/commit/?id=0c39134c
sci-electronics/yosys: add 0.60, drop 0.57
Signed-off-by: Huang Rui <vowstar <AT> gmail.com>
sci-electronics/yosys/Manifest | 2 +-
sci-electronics/yosys/{yosys-0.57.ebuild => yosys-0.60.ebuild} | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/sci-electronics/yosys/Manifest b/sci-electronics/yosys/Manifest
index 5eddffdc68..ef16a2a5b1 100644
--- a/sci-electronics/yosys/Manifest
+++ b/sci-electronics/yosys/Manifest
@@ -1 +1 @@
-DIST yosys-0.57.tar.gz 10657743 BLAKE2B
18cf66c70e41296f16e6c1cfa8743300bb6ea1d4c3d5177421291d53cfc08a9b070ce80b515c003bbbd4d05295b381737c1e17596f7849e1fc91bee32d3ac03b
SHA512
f856efb5d30ef445fbe7c42bd83136f960f5ca84959f06e6c5c1e2939f5dd895688ca194d66797b9335034b45675f3341770ef581f8d81bb8b0e711a8318852c
+DIST yosys-0.60.tar.gz 10765490 BLAKE2B
8c2cdde2a2891573e4c8176e38a1aa667136f82854b48730ad350bb5733ee4d3b30f347564ac4172636e427818d514083f17d84399cb41ef0151df4809d67416
SHA512
9f518f9eb28f4f92a31cd58a034df497ff8fe959ac72a756a452c3ab93b1075ef19889d65f014ae64ab4b7ef63d3d5dbc65828e2fcf81151576c3bf917ed7a08
diff --git a/sci-electronics/yosys/yosys-0.57.ebuild
b/sci-electronics/yosys/yosys-0.60.ebuild
similarity index 93%
rename from sci-electronics/yosys/yosys-0.57.ebuild
rename to sci-electronics/yosys/yosys-0.60.ebuild
index d6af411298..6aa8136901 100644
--- a/sci-electronics/yosys/yosys-0.57.ebuild
+++ b/sci-electronics/yosys/yosys-0.60.ebuild
@@ -4,7 +4,7 @@
EAPI=8
DESCRIPTION="framework for Verilog RTL synthesis"
-HOMEPAGE="http://www.clifford.at/yosys/";
+HOMEPAGE="https://yosyshq.net/yosys/";
SRC_URI="
https://github.com/YosysHQ/${PN}/releases/download/v${PV}/yosys.tar.gz
-> ${P}.tar.gz
"
