vapier 15/07/08 11:53:58
Added: powertop-2.7-skylake-2.patch
powertop-2.7-broadwell.patch
powertop-2.7-skylake.patch
powertop-2.7-braswell.patch
Log:
Add Intel Braswell/Broadwell/Skylake support from upstream.
(Portage version: 2.2.20/cvs/Linux x86_64, signed Manifest commit with key
D2E96200)
Revision Changes Path
1.1 sys-power/powertop/files/powertop-2.7-skylake-2.patch
file :
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-skylake-2.patch?rev=1.1&view=markup
plain:
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-skylake-2.patch?rev=1.1&content-type=text/plain
Index: powertop-2.7-skylake-2.patch
===================================================================
>From a7ddbd00f84253da38acc393e38f1c4db4263864 Mon Sep 17 00:00:00 2001
From: Alexandra Yates <alexandra.ya...@linux.intel.com>
Date: Thu, 16 Apr 2015 14:36:29 -0700
Subject: [PATCH] Add C7- C10 support for Intel SKY
Add C7 to C10 support for Intel SKY for CPU idle.
Signed-off-by: Alexandra Yates <alexandra.ya...@linux.intel.com>
---
src/cpu/intel_cpus.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel_cpus.cpp b/src/cpu/intel_cpus.cpp
index 72ecd50..d96cb49 100644
--- a/src/cpu/intel_cpus.cpp
+++ b/src/cpu/intel_cpus.cpp
@@ -63,7 +63,7 @@ static int intel_cpu_models[] = {
0x4C, /* BSW */
0x4D, /* AVN */
0x4F, /* BDX */
- 0x4E, /* Intel Next Generation */
+ 0x4E, /* SKY */
0x56, /* BDX-DE */
0 /* last entry must be zero */
};
@@ -318,7 +318,7 @@ nhm_package::nhm_package(int model)
has_c3_res = 1;
/* Haswell-ULT has C8/9/10*/
- if (model == 0x45 || model ==0x3D)
+ if (model == 0x45 || model == 0x3D || model == 0x4E)
has_c8c9c10_res = 1;
}
--
2.4.4
1.1 sys-power/powertop/files/powertop-2.7-broadwell.patch
file :
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-broadwell.patch?rev=1.1&view=markup
plain:
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-broadwell.patch?rev=1.1&content-type=text/plain
Index: powertop-2.7-broadwell.patch
===================================================================
>From 60258e6149a420b45521201e02f39cf41839e081 Mon Sep 17 00:00:00 2001
From: Alexandra Yates <alexandra.ya...@linux.intel.com>
Date: Wed, 22 Oct 2014 06:57:10 -0700
Subject: [PATCH] Enable PowerTOP support for: BSW, BDW-H
Added PowerTOP support for BSW and BDW-H platforms.
Signed-off-by: Alexandra Yates <alexandra.ya...@linux.intel.com>
---
src/cpu/intel_cpus.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/cpu/intel_cpus.cpp b/src/cpu/intel_cpus.cpp
index 167f1a7..d307aa1 100644
--- a/src/cpu/intel_cpus.cpp
+++ b/src/cpu/intel_cpus.cpp
@@ -59,6 +59,8 @@ static int intel_cpu_models[] = {
0x3D, /* Intel Next Generation */
0x3F, /* HSX */
0x46, /* HSW */
+ 0x47, /* BDW-H */
+ 0x4C, /* BSW */
0x4D, /* AVN */
0x4F, /* BDX */
0x56, /* BDX-DE */
--
2.4.4
1.1 sys-power/powertop/files/powertop-2.7-skylake.patch
file :
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-skylake.patch?rev=1.1&view=markup
plain:
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-skylake.patch?rev=1.1&content-type=text/plain
Index: powertop-2.7-skylake.patch
===================================================================
>From 761e87f1ccd3b5364b5518d7e29f4b7b8a6b8490 Mon Sep 17 00:00:00 2001
From: Alexandra Yates <alexandra.ya...@linux.intel.com>
Date: Wed, 21 Jan 2015 16:55:59 -0800
Subject: [PATCH] Adding support to SKY platforms.
Adding Intel SKY platform support to PowerTOP
Signed-off-by: Alexandra Yates <alexandra.ya...@linux.intel.com>
---
src/cpu/intel_cpus.cpp | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/cpu/intel_cpus.cpp b/src/cpu/intel_cpus.cpp
index d307aa1..04275e5 100644
--- a/src/cpu/intel_cpus.cpp
+++ b/src/cpu/intel_cpus.cpp
@@ -51,18 +51,19 @@ static int intel_cpu_models[] = {
0x2C, /* Westmere */
0x2A, /* SNB */
0x2D, /* SNB Xeon */
+ 0x37, /* BYT-M */
0x3A, /* IVB */
0x3C,
+ 0x3D, /* Broadwell */
0x3E, /* IVB Xeon */
- 0x37, /* BYT-M */
- 0x45, /* HSW-ULT */
- 0x3D, /* Intel Next Generation */
0x3F, /* HSX */
+ 0x45, /* HSW-ULT */
0x46, /* HSW */
0x47, /* BDW-H */
0x4C, /* BSW */
0x4D, /* AVN */
0x4F, /* BDX */
+ 0x4E, /* Intel Next Generation */
0x56, /* BDX-DE */
0 /* last entry must be zero */
};
@@ -125,6 +126,7 @@ nhm_core::nhm_core(int model)
case 0x3C:
case 0x3E: /* IVB Xeon */
case 0x45: /* HSW-ULT */
+ case 0x4E: /* SKY */
case 0x3D: /* Intel Next Generation */
has_c7_res = 1;
}
@@ -300,6 +302,7 @@ nhm_package::nhm_package(int model)
case 0x3C:
case 0x3E: /* IVB Xeon */
case 0x45: /* HSW-ULT */
+ case 0x4E: /* SKY */
case 0x3D: /* Intel Next Generation */
has_c2c6_res=1;
has_c7_res = 1;
--
2.4.4
1.1 sys-power/powertop/files/powertop-2.7-braswell.patch
file :
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-braswell.patch?rev=1.1&view=markup
plain:
http://sources.gentoo.org/viewvc.cgi/gentoo-x86/sys-power/powertop/files/powertop-2.7-braswell.patch?rev=1.1&content-type=text/plain
Index: powertop-2.7-braswell.patch
===================================================================
>From 1c60f2342b752149f3d6543c63fee11a167dc998 Mon Sep 17 00:00:00 2001
From: "David E. Box" <david.e....@linux.intel.com>
Date: Thu, 2 Apr 2015 21:24:29 -0700
Subject: [PATCH] Fix Powertop support for Intel Braswell SOC
Correct Braswell MSR used to determine PC6 residency.
Signed-off-by: David E. Box <david.e....@linux.intel.com>
---
src/cpu/intel_cpus.cpp | 21 +++++++++++++++++++--
src/cpu/intel_cpus.h | 1 +
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel_cpus.cpp b/src/cpu/intel_cpus.cpp
index d96cb49..1f3647a 100644
--- a/src/cpu/intel_cpus.cpp
+++ b/src/cpu/intel_cpus.cpp
@@ -289,6 +289,7 @@ nhm_package::nhm_package(int model)
has_c8c9c10_res = 0;
has_c2c6_res = 0;
has_c7_res = 0;
+ has_c6c_res = 0;
switch(model) {
case 0x2A: /* SNB */
@@ -314,6 +315,9 @@ nhm_package::nhm_package(int model)
else
has_c7_res = 0;
}
+ /* BSW only exposes package C6 */
+ else if (model == 0x4C)
+ has_c6c_res = 1;
else
has_c3_res = 1;
@@ -360,7 +364,15 @@ void nhm_package::measurement_start(void)
if (this->has_c3_res)
c3_before = get_msr(number, MSR_PKG_C3_RESIDENCY);
- c6_before = get_msr(number, MSR_PKG_C6_RESIDENCY);
+
+ /*
+ * Hack for Braswell where C7 MSR is actually BSW C6
+ */
+ if (this->has_c6c_res)
+ c6_before = get_msr(number, MSR_PKG_C7_RESIDENCY);
+ else
+ c6_before = get_msr(number, MSR_PKG_C6_RESIDENCY);
+
if (this->has_c7_res)
c7_before = get_msr(number, MSR_PKG_C7_RESIDENCY);
if (this->has_c8c9c10_res) {
@@ -401,7 +413,12 @@ void nhm_package::measurement_end(void)
if (this->has_c3_res)
c3_after = get_msr(number, MSR_PKG_C3_RESIDENCY);
- c6_after = get_msr(number, MSR_PKG_C6_RESIDENCY);
+
+ if (this->has_c6c_res)
+ c6_after = get_msr(number, MSR_PKG_C7_RESIDENCY);
+ else
+ c6_after = get_msr(number, MSR_PKG_C6_RESIDENCY);
+
if (this->has_c7_res)
c7_after = get_msr(number, MSR_PKG_C7_RESIDENCY);
if (has_c8c9c10_res) {
diff --git a/src/cpu/intel_cpus.h b/src/cpu/intel_cpus.h
index 810a243..0331069 100644
--- a/src/cpu/intel_cpus.h
+++ b/src/cpu/intel_cpus.h
@@ -77,6 +77,7 @@ public:
int has_c7_res;
int has_c2c6_res;
int has_c3_res;
+ int has_c6c_res; /* BSW */
int has_c8c9c10_res;
nhm_package(int model);
virtual void measurement_start(void);
--
2.4.4
