commit: f04f7d5137cc4c1e2123c3d450b3e92165cd78fe Author: Mike Pagano <mpagano <AT> gentoo <DOT> org> AuthorDate: Mon Oct 23 16:31:25 2017 +0000 Commit: Mike Pagano <mpagano <AT> gentoo <DOT> org> CommitDate: Mon Oct 23 16:31:25 2017 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=f04f7d51
Linux 4.14. Patch to support for namespace user.pax.* on tmpfs. Patch to enable link security restrictions by default. Patch that provides Workaround to enable poweroff on Mac Pro 11. See bug #601964. hid-apple patch that enables swapping of the FN and left Control keys and some additional on some apple keyboards. Patch to ensure that /dev/root doesn't appear in /proc/mounts when bootint without an initramfs. Patch to enable control of the unaligned access control policy from sysctl. Patch that adds Gentoo Linux support config settings and defaults. Kernel patch that enables gcc >= v4.9 optimizations for additional CPUs. 0000_README | 29 ++ 1500_XATTR_USER_PREFIX.patch | 69 +++ ...ble-link-security-restrictions-by-default.patch | 22 + 2300_enable-poweroff-on-Mac-Pro-11.patch | 76 +++ 2600_enable-key-swapping-for-apple-mac.patch | 114 +++++ 2900_dev-root-proc-mount-fix.patch | 38 ++ 4400_alpha-sysctl-uac.patch | 142 ++++++ ...able-additional-cpu-optimizations-for-gcc.patch | 530 +++++++++++++++++++++ 8 files changed, 1020 insertions(+) diff --git a/0000_README b/0000_README index 9018993..6bcc0b5 100644 --- a/0000_README +++ b/0000_README @@ -43,6 +43,35 @@ EXPERIMENTAL Individual Patch Descriptions: -------------------------------------------------------------------------- +Patch: 1500_XATTR_USER_PREFIX.patch +From: https://bugs.gentoo.org/show_bug.cgi?id=470644 +Desc: Support for namespace user.pax.* on tmpfs. + +Patch: 1510_fs-enable-link-security-restrictions-by-default.patch +From: http://sources.debian.net/src/linux/3.16.7-ckt4-3/debian/patches/debian/fs-enable-link-security-restrictions-by-default.patch/ +Desc: Enable link security restrictions by default. + +Patch: 2300_enable-poweroff-on-Mac-Pro-11.patch +From: http://kernel.ubuntu.com/git/ubuntu/ubuntu-xenial.git/patch/drivers/pci/quirks.c?id=5080ff61a438f3dd80b88b423e1a20791d8a774c +Desc: Workaround to enable poweroff on Mac Pro 11. See bug #601964. + +Patch: 2600_enable-key-swapping-for-apple-mac.patch +From: https://github.com/free5lot/hid-apple-patched +Desc: This hid-apple patch enables swapping of the FN and left Control keys and some additional on some apple keyboards. See bug #622902 + +Patch: 2900_dev-root-proc-mount-fix.patch +From: https://bugs.gentoo.org/show_bug.cgi?id=438380 +Desc: Ensure that /dev/root doesn't appear in /proc/mounts when bootint without an initramfs. + +Patch: 4400_alpha-sysctl-uac.patch +From: Tobias Klausmann (klaus...@gentoo.org) and http://bugs.gentoo.org/show_bug.cgi?id=217323 +Desc: Enable control of the unaligned access control policy from sysctl + Patch: 4567_distro-Gentoo-Kconfig.patch From: Tom Wijsman <tom...@gentoo.org> Desc: Add Gentoo Linux support config settings and defaults. + +Patch: 5010_enable-additional-cpu-optimizations-for-gcc.patch +From: https://github.com/graysky2/kernel_gcc_patch/ +Desc: Kernel patch enables gcc >= v4.9 optimizations for additional CPUs. + diff --git a/1500_XATTR_USER_PREFIX.patch b/1500_XATTR_USER_PREFIX.patch new file mode 100644 index 0000000..bacd032 --- /dev/null +++ b/1500_XATTR_USER_PREFIX.patch @@ -0,0 +1,69 @@ +From: Anthony G. Basile <bluen...@gentoo.org> + +This patch adds support for a restricted user-controlled namespace on +tmpfs filesystem used to house PaX flags. The namespace must be of the +form user.pax.* and its value cannot exceed a size of 8 bytes. + +This is needed even on all Gentoo systems so that XATTR_PAX flags +are preserved for users who might build packages using portage on +a tmpfs system with a non-hardened kernel and then switch to a +hardened kernel with XATTR_PAX enabled. + +The namespace is added to any user with Extended Attribute support +enabled for tmpfs. Users who do not enable xattrs will not have +the XATTR_PAX flags preserved. + +diff --git a/include/uapi/linux/xattr.h b/include/uapi/linux/xattr.h +index 1590c49..5eab462 100644 +--- a/include/uapi/linux/xattr.h ++++ b/include/uapi/linux/xattr.h +@@ -73,5 +73,9 @@ + #define XATTR_POSIX_ACL_DEFAULT "posix_acl_default" + #define XATTR_NAME_POSIX_ACL_DEFAULT XATTR_SYSTEM_PREFIX XATTR_POSIX_ACL_DEFAULT + ++/* User namespace */ ++#define XATTR_PAX_PREFIX XATTR_USER_PREFIX "pax." ++#define XATTR_PAX_FLAGS_SUFFIX "flags" ++#define XATTR_NAME_PAX_FLAGS XATTR_PAX_PREFIX XATTR_PAX_FLAGS_SUFFIX + + #endif /* _UAPI_LINUX_XATTR_H */ +diff --git a/mm/shmem.c b/mm/shmem.c +index 440e2a7..c377172 100644 +--- a/mm/shmem.c ++++ b/mm/shmem.c +@@ -2667,6 +2667,14 @@ static int shmem_xattr_handler_set(const struct xattr_handler *handler, + struct shmem_inode_info *info = SHMEM_I(d_inode(dentry)); + + name = xattr_full_name(handler, name); ++ ++ if (!strncmp(name, XATTR_USER_PREFIX, XATTR_USER_PREFIX_LEN)) { ++ if (strcmp(name, XATTR_NAME_PAX_FLAGS)) ++ return -EOPNOTSUPP; ++ if (size > 8) ++ return -EINVAL; ++ } ++ + return simple_xattr_set(&info->xattrs, name, value, size, flags); + } + +@@ -2682,6 +2690,12 @@ static const struct xattr_handler shmem_trusted_xattr_handler = { + .set = shmem_xattr_handler_set, + }; + ++static const struct xattr_handler shmem_user_xattr_handler = { ++ .prefix = XATTR_USER_PREFIX, ++ .get = shmem_xattr_handler_get, ++ .set = shmem_xattr_handler_set, ++}; ++ + static const struct xattr_handler *shmem_xattr_handlers[] = { + #ifdef CONFIG_TMPFS_POSIX_ACL + &posix_acl_access_xattr_handler, +@@ -2689,6 +2703,7 @@ static const struct xattr_handler *shmem_xattr_handlers[] = { + #endif + &shmem_security_xattr_handler, + &shmem_trusted_xattr_handler, ++ &shmem_user_xattr_handler, + NULL + }; + diff --git a/1510_fs-enable-link-security-restrictions-by-default.patch b/1510_fs-enable-link-security-restrictions-by-default.patch new file mode 100644 index 0000000..639fb3c --- /dev/null +++ b/1510_fs-enable-link-security-restrictions-by-default.patch @@ -0,0 +1,22 @@ +From: Ben Hutchings <b...@decadent.org.uk> +Subject: fs: Enable link security restrictions by default +Date: Fri, 02 Nov 2012 05:32:06 +0000 +Bug-Debian: https://bugs.debian.org/609455 +Forwarded: not-needed + +This reverts commit 561ec64ae67ef25cac8d72bb9c4bfc955edfd415 +('VFS: don't do protected {sym,hard}links by default'). + +--- a/fs/namei.c ++++ b/fs/namei.c +@@ -651,8 +651,8 @@ static inline void put_link(struct namei + path_put(link); + } + +-int sysctl_protected_symlinks __read_mostly = 0; +-int sysctl_protected_hardlinks __read_mostly = 0; ++int sysctl_protected_symlinks __read_mostly = 1; ++int sysctl_protected_hardlinks __read_mostly = 1; + + /** + * may_follow_link - Check symlink following for unsafe situations diff --git a/2300_enable-poweroff-on-Mac-Pro-11.patch b/2300_enable-poweroff-on-Mac-Pro-11.patch new file mode 100644 index 0000000..063f2a1 --- /dev/null +++ b/2300_enable-poweroff-on-Mac-Pro-11.patch @@ -0,0 +1,76 @@ +From 5080ff61a438f3dd80b88b423e1a20791d8a774c Mon Sep 17 00:00:00 2001 +From: Chen Yu <yu.c.c...@intel.com> +Date: Fri, 19 Aug 2016 10:25:57 -0700 +Subject: UBUNTU: SAUCE: PCI: Workaround to enable poweroff on Mac Pro 11 + +BugLink: http://bugs.launchpad.net/bugs/1587714 + +People reported that they can not do a poweroff nor a +suspend to ram on their Mac Pro 11. After some investigations +it was found that, once the PCI bridge 0000:00:1c.0 reassigns its +mm windows to ([mem 0x7fa00000-0x7fbfffff] and +[mem 0x7fc00000-0x7fdfffff 64bit pref]), the region of ACPI +io resource 0x1804 becomes unaccessible immediately, where the +ACPI Sleep register is located, as a result neither poweroff(S5) +nor suspend to ram(S3) works. + +As suggested by Bjorn, further testing shows that, there is an +unreported device may be (using) conflict with above aperture, +which brings unpredictable result such as the failure of accessing +the io port, which blocks the poweroff(S5). Besides if we reassign +the memory aperture to the other place, the poweroff works again. + +As we do not find any resource declared in _CRS which contain above +memory aperture, and Mac OS does not use this pci bridge neither, we +choose a simple workaround to clear the hotplug flag(suggested by +Yinghai Lu), thus do not allocate any resource for this pci bridge, +and thereby no conflict anymore. + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=103211 +Cc: Bjorn Helgaas <bhelg...@google.com> +Cc: Rafael J. Wysocki <raf...@kernel.org> +Cc: Lukas Wunner <lu...@wunner.de> +Signed-off-by: Chen Yu <yu.c.c...@intel.com> +Reference: https://patchwork.kernel.org/patch/9289777/ +Signed-off-by: Kamal Mostafa <ka...@canonical.com> +Acked-by: Brad Figg <brad.f...@canonical.com> +Acked-by: Stefan Bader <stefan.ba...@canonical.com> +Signed-off-by: Tim Gardner <tim.gard...@canonical.com> +--- + drivers/pci/quirks.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 48cfaa0..23968b6 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -2750,6 +2750,26 @@ static void quirk_hotplug_bridge(struct pci_dev *dev) + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); + + /* ++ * Apple: Avoid programming the memory/io aperture of 00:1c.0 ++ * ++ * BIOS does not declare any resource for 00:1c.0, but with ++ * hotplug flag set, thus the OS allocates: ++ * [mem 0x7fa00000 - 0x7fbfffff] ++ * [mem 0x7fc00000-0x7fdfffff 64bit pref] ++ * which is conflict with an unreported device, which ++ * causes unpredictable result such as accessing io port. ++ * So clear the hotplug flag to work around it. ++ */ ++static void quirk_apple_mbp_poweroff(struct pci_dev *dev) ++{ ++ if (dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,4") || ++ dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,5")) ++ dev->is_hotplug_bridge = 0; ++} ++ ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); ++ ++/* + * This is a quirk for the Ricoh MMC controller found as a part of + * some mulifunction chips. + +-- +cgit v0.11.2 + diff --git a/2600_enable-key-swapping-for-apple-mac.patch b/2600_enable-key-swapping-for-apple-mac.patch new file mode 100644 index 0000000..ab228d3 --- /dev/null +++ b/2600_enable-key-swapping-for-apple-mac.patch @@ -0,0 +1,114 @@ +--- a/drivers/hid/hid-apple.c ++++ b/drivers/hid/hid-apple.c +@@ -52,6 +52,22 @@ + "(For people who want to keep Windows PC keyboard muscle memory. " + "[0] = as-is, Mac layout. 1 = swapped, Windows layout.)"); + ++static unsigned int swap_fn_leftctrl; ++module_param(swap_fn_leftctrl, uint, 0644); ++MODULE_PARM_DESC(swap_fn_leftctrl, "Swap the Fn and left Control keys. " ++ "(For people who want to keep PC keyboard muscle memory. " ++ "[0] = as-is, Mac layout, 1 = swapped, PC layout)"); ++ ++static unsigned int rightalt_as_rightctrl; ++module_param(rightalt_as_rightctrl, uint, 0644); ++MODULE_PARM_DESC(rightalt_as_rightctrl, "Use the right Alt key as a right Ctrl key. " ++ "[0] = as-is, Mac layout. 1 = Right Alt is right Ctrl"); ++ ++static unsigned int ejectcd_as_delete; ++module_param(ejectcd_as_delete, uint, 0644); ++MODULE_PARM_DESC(ejectcd_as_delete, "Use Eject-CD key as Delete key. " ++ "([0] = disabled, 1 = enabled)"); ++ + struct apple_sc { + unsigned long quirks; + unsigned int fn_on; +@@ -164,6 +180,21 @@ + { } + }; + ++static const struct apple_key_translation swapped_fn_leftctrl_keys[] = { ++ { KEY_FN, KEY_LEFTCTRL }, ++ { } ++}; ++ ++static const struct apple_key_translation rightalt_as_rightctrl_keys[] = { ++ { KEY_RIGHTALT, KEY_RIGHTCTRL }, ++ { } ++}; ++ ++static const struct apple_key_translation ejectcd_as_delete_keys[] = { ++ { KEY_EJECTCD, KEY_DELETE }, ++ { } ++}; ++ + static const struct apple_key_translation *apple_find_translation( + const struct apple_key_translation *table, u16 from) + { +@@ -183,9 +214,11 @@ + struct apple_sc *asc = hid_get_drvdata(hid); + const struct apple_key_translation *trans, *table; + +- if (usage->code == KEY_FN) { ++ u16 fn_keycode = (swap_fn_leftctrl) ? (KEY_LEFTCTRL) : (KEY_FN); ++ ++ if (usage->code == fn_keycode) { + asc->fn_on = !!value; +- input_event(input, usage->type, usage->code, value); ++ input_event(input, usage->type, KEY_FN, value); + return 1; + } + +@@ -264,6 +297,30 @@ + } + } + ++ if (swap_fn_leftctrl) { ++ trans = apple_find_translation(swapped_fn_leftctrl_keys, usage->code); ++ if (trans) { ++ input_event(input, usage->type, trans->to, value); ++ return 1; ++ } ++ } ++ ++ if (ejectcd_as_delete) { ++ trans = apple_find_translation(ejectcd_as_delete_keys, usage->code); ++ if (trans) { ++ input_event(input, usage->type, trans->to, value); ++ return 1; ++ } ++ } ++ ++ if (rightalt_as_rightctrl) { ++ trans = apple_find_translation(rightalt_as_rightctrl_keys, usage->code); ++ if (trans) { ++ input_event(input, usage->type, trans->to, value); ++ return 1; ++ } ++ } ++ + return 0; + } + +@@ -327,6 +384,21 @@ + + for (trans = apple_iso_keyboard; trans->from; trans++) + set_bit(trans->to, input->keybit); ++ ++ if (swap_fn_leftctrl) { ++ for (trans = swapped_fn_leftctrl_keys; trans->from; trans++) ++ set_bit(trans->to, input->keybit); ++ } ++ ++ if (ejectcd_as_delete) { ++ for (trans = ejectcd_as_delete_keys; trans->from; trans++) ++ set_bit(trans->to, input->keybit); ++ } ++ ++ if (rightalt_as_rightctrl) { ++ for (trans = rightalt_as_rightctrl_keys; trans->from; trans++) ++ set_bit(trans->to, input->keybit); ++ } + } + + static int apple_input_mapping(struct hid_device *hdev, struct hid_input *hi, diff --git a/2900_dev-root-proc-mount-fix.patch b/2900_dev-root-proc-mount-fix.patch new file mode 100644 index 0000000..60af1eb --- /dev/null +++ b/2900_dev-root-proc-mount-fix.patch @@ -0,0 +1,38 @@ +--- a/init/do_mounts.c 2015-08-19 10:27:16.753852576 -0400 ++++ b/init/do_mounts.c 2015-08-19 10:34:25.473850353 -0400 +@@ -490,7 +490,11 @@ void __init change_floppy(char *fmt, ... + va_start(args, fmt); + vsprintf(buf, fmt, args); + va_end(args); +- fd = sys_open("/dev/root", O_RDWR | O_NDELAY, 0); ++ if (saved_root_name[0]) ++ fd = sys_open(saved_root_name, O_RDWR | O_NDELAY, 0); ++ else ++ fd = sys_open("/dev/root", O_RDWR | O_NDELAY, 0); ++ + if (fd >= 0) { + sys_ioctl(fd, FDEJECT, 0); + sys_close(fd); +@@ -534,11 +538,17 @@ void __init mount_root(void) + #endif + #ifdef CONFIG_BLOCK + { +- int err = create_dev("/dev/root", ROOT_DEV); +- +- if (err < 0) +- pr_emerg("Failed to create /dev/root: %d\n", err); +- mount_block_root("/dev/root", root_mountflags); ++ if (saved_root_name[0] == '/') { ++ int err = create_dev(saved_root_name, ROOT_DEV); ++ if (err < 0) ++ pr_emerg("Failed to create %s: %d\n", saved_root_name, err); ++ mount_block_root(saved_root_name, root_mountflags); ++ } else { ++ int err = create_dev("/dev/root", ROOT_DEV); ++ if (err < 0) ++ pr_emerg("Failed to create /dev/root: %d\n", err); ++ mount_block_root("/dev/root", root_mountflags); ++ } + } + #endif + } diff --git a/4400_alpha-sysctl-uac.patch b/4400_alpha-sysctl-uac.patch new file mode 100644 index 0000000..d42b4ed --- /dev/null +++ b/4400_alpha-sysctl-uac.patch @@ -0,0 +1,142 @@ +diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig +index 7f312d8..1eb686b 100644 +--- a/arch/alpha/Kconfig ++++ b/arch/alpha/Kconfig +@@ -697,6 +697,33 @@ config HZ + default 1200 if HZ_1200 + default 1024 + ++config ALPHA_UAC_SYSCTL ++ bool "Configure UAC policy via sysctl" ++ depends on SYSCTL ++ default y ++ ---help--- ++ Configuring the UAC (unaligned access control) policy on a Linux ++ system usually involves setting a compile time define. If you say ++ Y here, you will be able to modify the UAC policy at runtime using ++ the /proc interface. ++ ++ The UAC policy defines the action Linux should take when an ++ unaligned memory access occurs. The action can include printing a ++ warning message (NOPRINT), sending a signal to the offending ++ program to help developers debug their applications (SIGBUS), or ++ disabling the transparent fixing (NOFIX). ++ ++ The sysctls will be initialized to the compile-time defined UAC ++ policy. You can change these manually, or with the sysctl(8) ++ userspace utility. ++ ++ To disable the warning messages at runtime, you would use ++ ++ echo 1 > /proc/sys/kernel/uac/noprint ++ ++ This is pretty harmless. Say Y if you're not sure. ++ ++ + source "drivers/pci/Kconfig" + source "drivers/eisa/Kconfig" + +diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c +index 74aceea..cb35d80 100644 +--- a/arch/alpha/kernel/traps.c ++++ b/arch/alpha/kernel/traps.c +@@ -103,6 +103,49 @@ static char * ireg_name[] = {"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "t10", "t11", "ra", "pv", "at", "gp", "sp", "zero"}; + #endif + ++#ifdef CONFIG_ALPHA_UAC_SYSCTL ++ ++#include <linux/sysctl.h> ++ ++static int enabled_noprint = 0; ++static int enabled_sigbus = 0; ++static int enabled_nofix = 0; ++ ++struct ctl_table uac_table[] = { ++ { ++ .procname = "noprint", ++ .data = &enabled_noprint, ++ .maxlen = sizeof (int), ++ .mode = 0644, ++ .proc_handler = &proc_dointvec, ++ }, ++ { ++ .procname = "sigbus", ++ .data = &enabled_sigbus, ++ .maxlen = sizeof (int), ++ .mode = 0644, ++ .proc_handler = &proc_dointvec, ++ }, ++ { ++ .procname = "nofix", ++ .data = &enabled_nofix, ++ .maxlen = sizeof (int), ++ .mode = 0644, ++ .proc_handler = &proc_dointvec, ++ }, ++ { } ++}; ++ ++static int __init init_uac_sysctl(void) ++{ ++ /* Initialize sysctls with the #defined UAC policy */ ++ enabled_noprint = (test_thread_flag (TS_UAC_NOPRINT)) ? 1 : 0; ++ enabled_sigbus = (test_thread_flag (TS_UAC_SIGBUS)) ? 1 : 0; ++ enabled_nofix = (test_thread_flag (TS_UAC_NOFIX)) ? 1 : 0; ++ return 0; ++} ++#endif ++ + static void + dik_show_code(unsigned int *pc) + { +@@ -785,7 +828,12 @@ do_entUnaUser(void __user * va, unsigned long opcode, + /* Check the UAC bits to decide what the user wants us to do + with the unaliged access. */ + ++#ifndef CONFIG_ALPHA_UAC_SYSCTL + if (!(current_thread_info()->status & TS_UAC_NOPRINT)) { ++#else /* CONFIG_ALPHA_UAC_SYSCTL */ ++ if (!(current_thread_info()->status & TS_UAC_NOPRINT) && ++ !(enabled_noprint)) { ++#endif /* CONFIG_ALPHA_UAC_SYSCTL */ + if (__ratelimit(&ratelimit)) { + printk("%s(%d): unaligned trap at %016lx: %p %lx %ld\n", + current->comm, task_pid_nr(current), +@@ -1090,3 +1138,6 @@ trap_init(void) + wrent(entSys, 5); + wrent(entDbg, 6); + } ++#ifdef CONFIG_ALPHA_UAC_SYSCTL ++ __initcall(init_uac_sysctl); ++#endif +diff --git a/kernel/sysctl.c b/kernel/sysctl.c +index 87b2fc3..55021a8 100644 +--- a/kernel/sysctl.c ++++ b/kernel/sysctl.c +@@ -152,6 +152,11 @@ static unsigned long hung_task_timeout_max = (LONG_MAX/HZ); + #ifdef CONFIG_INOTIFY_USER + #include <linux/inotify.h> + #endif ++ ++#ifdef CONFIG_ALPHA_UAC_SYSCTL ++extern struct ctl_table uac_table[]; ++#endif ++ + #ifdef CONFIG_SPARC + #endif + +@@ -1844,6 +1849,13 @@ static struct ctl_table debug_table[] = { + .extra2 = &one, + }, + #endif ++#ifdef CONFIG_ALPHA_UAC_SYSCTL ++ { ++ .procname = "uac", ++ .mode = 0555, ++ .child = uac_table, ++ }, ++#endif /* CONFIG_ALPHA_UAC_SYSCTL */ + { } + }; + diff --git a/5010_enable-additional-cpu-optimizations-for-gcc.patch b/5010_enable-additional-cpu-optimizations-for-gcc.patch new file mode 100644 index 0000000..c68d072 --- /dev/null +++ b/5010_enable-additional-cpu-optimizations-for-gcc.patch @@ -0,0 +1,530 @@ +WARNING +This patch works with gcc versions 4.9+ and with kernel version 3.15+ and should +NOT be applied when compiling on older versions of gcc due to key name changes +of the march flags introduced with the version 4.9 release of gcc.[1] + +Use the older version of this patch hosted on the same github for older +versions of gcc. + +FEATURES +This patch adds additional CPU options to the Linux kernel accessible under: + Processor type and features ---> + Processor family ---> + +The expanded microarchitectures include: +* AMD Improved K8-family +* AMD K10-family +* AMD Family 10h (Barcelona) +* AMD Family 14h (Bobcat) +* AMD Family 16h (Jaguar) +* AMD Family 15h (Bulldozer) +* AMD Family 15h (Piledriver) +* AMD Family 15h (Steamroller) +* AMD Family 15h (Excavator) +* AMD Family 17h (Zen) +* Intel Silvermont low-power processors +* Intel 1st Gen Core i3/i5/i7 (Nehalem) +* Intel 1.5 Gen Core i3/i5/i7 (Westmere) +* Intel 2nd Gen Core i3/i5/i7 (Sandybridge) +* Intel 3rd Gen Core i3/i5/i7 (Ivybridge) +* Intel 4th Gen Core i3/i5/i7 (Haswell) +* Intel 5th Gen Core i3/i5/i7 (Broadwell) +* Intel 6th Gen Core i3/i5.i7 (Skylake) + +It also offers to compile passing the 'native' option which, "selects the CPU +to generate code for at compilation time by determining the processor type of +the compiling machine. Using -march=native enables all instruction subsets +supported by the local machine and will produce code optimized for the local +machine under the constraints of the selected instruction set."[3] + +MINOR NOTES +This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9 +changes. Note that upstream is using the deprecated 'match=atom' flags when I +believe it should use the newer 'march=bonnell' flag for atom processors.[2] + +It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The +recommendation is use to the 'atom' option instead. + +BENEFITS +Small but real speed increases are measurable using a make endpoint comparing +a generic kernel to one built with one of the respective microarchs. + +See the following experimental evidence supporting this statement: +https://github.com/graysky2/kernel_gcc_patch + +REQUIREMENTS +linux version >=3.15 +gcc version >=4.9 + +ACKNOWLEDGMENTS +This patch builds on the seminal work by Jeroen.[5] + +REFERENCES +1. https://gcc.gnu.org/gcc-4.9/changes.html +2. https://bugzilla.kernel.org/show_bug.cgi?id=77461 +3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html +4. https://github.com/graysky2/kernel_gcc_patch/issues/15 +5. http://www.linuxforge.net/docs/linux/linux-gcc.php + +--- a/arch/x86/include/asm/module.h 2017-08-02 11:41:47.442200461 -0400 ++++ b/arch/x86/include/asm/module.h 2017-08-02 12:14:21.204358744 -0400 +@@ -15,6 +15,24 @@ + #define MODULE_PROC_FAMILY "586MMX " + #elif defined CONFIG_MCORE2 + #define MODULE_PROC_FAMILY "CORE2 " ++#elif defined CONFIG_MNATIVE ++#define MODULE_PROC_FAMILY "NATIVE " ++#elif defined CONFIG_MNEHALEM ++#define MODULE_PROC_FAMILY "NEHALEM " ++#elif defined CONFIG_MWESTMERE ++#define MODULE_PROC_FAMILY "WESTMERE " ++#elif defined CONFIG_MSILVERMONT ++#define MODULE_PROC_FAMILY "SILVERMONT " ++#elif defined CONFIG_MSANDYBRIDGE ++#define MODULE_PROC_FAMILY "SANDYBRIDGE " ++#elif defined CONFIG_MIVYBRIDGE ++#define MODULE_PROC_FAMILY "IVYBRIDGE " ++#elif defined CONFIG_MHASWELL ++#define MODULE_PROC_FAMILY "HASWELL " ++#elif defined CONFIG_MBROADWELL ++#define MODULE_PROC_FAMILY "BROADWELL " ++#elif defined CONFIG_MSKYLAKE ++#define MODULE_PROC_FAMILY "SKYLAKE " + #elif defined CONFIG_MATOM + #define MODULE_PROC_FAMILY "ATOM " + #elif defined CONFIG_M686 +@@ -33,6 +51,26 @@ + #define MODULE_PROC_FAMILY "K7 " + #elif defined CONFIG_MK8 + #define MODULE_PROC_FAMILY "K8 " ++#elif defined CONFIG_MK8SSE3 ++#define MODULE_PROC_FAMILY "K8SSE3 " ++#elif defined CONFIG_MK10 ++#define MODULE_PROC_FAMILY "K10 " ++#elif defined CONFIG_MBARCELONA ++#define MODULE_PROC_FAMILY "BARCELONA " ++#elif defined CONFIG_MBOBCAT ++#define MODULE_PROC_FAMILY "BOBCAT " ++#elif defined CONFIG_MBULLDOZER ++#define MODULE_PROC_FAMILY "BULLDOZER " ++#elif defined CONFIG_MPILEDRIVER ++#define MODULE_PROC_FAMILY "PILEDRIVER " ++#elif defined CONFIG_MSTEAMROLLER ++#define MODULE_PROC_FAMILY "STEAMROLLER " ++#elif defined CONFIG_MJAGUAR ++#define MODULE_PROC_FAMILY "JAGUAR " ++#elif defined CONFIG_MEXCAVATOR ++#define MODULE_PROC_FAMILY "EXCAVATOR " ++#elif defined CONFIG_MZEN ++#define MODULE_PROC_FAMILY "ZEN " + #elif defined CONFIG_MELAN + #define MODULE_PROC_FAMILY "ELAN " + #elif defined CONFIG_MCRUSOE +--- a/arch/x86/Kconfig.cpu 2017-08-02 11:41:47.443200463 -0400 ++++ b/arch/x86/Kconfig.cpu 2017-08-02 12:14:37.108956741 -0400 +@@ -115,6 +115,7 @@ config MPENTIUMM + config MPENTIUM4 + bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" + depends on X86_32 ++ select X86_P6_NOP + ---help--- + Select this for Intel Pentium 4 chips. This includes the + Pentium 4, Pentium D, P4-based Celeron and Xeon, and +@@ -147,9 +148,8 @@ config MPENTIUM4 + -Paxville + -Dempsey + +- + config MK6 +- bool "K6/K6-II/K6-III" ++ bool "AMD K6/K6-II/K6-III" + depends on X86_32 + ---help--- + Select this for an AMD K6-family processor. Enables use of +@@ -157,7 +157,7 @@ config MK6 + flags to GCC. + + config MK7 +- bool "Athlon/Duron/K7" ++ bool "AMD Athlon/Duron/K7" + depends on X86_32 + ---help--- + Select this for an AMD Athlon K7-family processor. Enables use of +@@ -165,12 +165,83 @@ config MK7 + flags to GCC. + + config MK8 +- bool "Opteron/Athlon64/Hammer/K8" ++ bool "AMD Opteron/Athlon64/Hammer/K8" + ---help--- + Select this for an AMD Opteron or Athlon64 Hammer-family processor. + Enables use of some extended instructions, and passes appropriate + optimization flags to GCC. + ++config MK8SSE3 ++ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3" ++ ---help--- ++ Select this for improved AMD Opteron or Athlon64 Hammer-family processors. ++ Enables use of some extended instructions, and passes appropriate ++ optimization flags to GCC. ++ ++config MK10 ++ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10" ++ ---help--- ++ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50, ++ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor. ++ Enables use of some extended instructions, and passes appropriate ++ optimization flags to GCC. ++ ++config MBARCELONA ++ bool "AMD Barcelona" ++ ---help--- ++ Select this for AMD Family 10h Barcelona processors. ++ ++ Enables -march=barcelona ++ ++config MBOBCAT ++ bool "AMD Bobcat" ++ ---help--- ++ Select this for AMD Family 14h Bobcat processors. ++ ++ Enables -march=btver1 ++ ++config MJAGUAR ++ bool "AMD Jaguar" ++ ---help--- ++ Select this for AMD Family 16h Jaguar processors. ++ ++ Enables -march=btver2 ++ ++config MBULLDOZER ++ bool "AMD Bulldozer" ++ ---help--- ++ Select this for AMD Family 15h Bulldozer processors. ++ ++ Enables -march=bdver1 ++ ++config MPILEDRIVER ++ bool "AMD Piledriver" ++ ---help--- ++ Select this for AMD Family 15h Piledriver processors. ++ ++ Enables -march=bdver2 ++ ++config MSTEAMROLLER ++ bool "AMD Steamroller" ++ ---help--- ++ Select this for AMD Family 15h Steamroller processors. ++ ++ Enables -march=bdver3 ++ ++config MEXCAVATOR ++ bool "AMD Excavator" ++ ---help--- ++ Select this for AMD Family 15h Excavator processors. ++ ++ Enables -march=bdver4 ++ ++config MZEN ++ bool "AMD Zen" ++ ---help--- ++ Select this for AMD Family 17h Zen processors. ++ ++ Enables -march=znver1 ++ + config MCRUSOE + bool "Crusoe" + depends on X86_32 +@@ -252,6 +323,7 @@ config MVIAC7 + + config MPSC + bool "Intel P4 / older Netburst based Xeon" ++ select X86_P6_NOP + depends on X86_64 + ---help--- + Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey +@@ -261,8 +333,19 @@ config MPSC + using the cpu family field + in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. + ++config MATOM ++ bool "Intel Atom" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for the Intel Atom platform. Intel Atom CPUs have an ++ in-order pipelining architecture and thus can benefit from ++ accordingly optimized code. Use a recent GCC with specific Atom ++ support in order to fully benefit from selecting this option. ++ + config MCORE2 +- bool "Core 2/newer Xeon" ++ bool "Intel Core 2" ++ select X86_P6_NOP + ---help--- + + Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and +@@ -270,14 +353,79 @@ config MCORE2 + family in /proc/cpuinfo. Newer ones have 6 and older ones 15 + (not a typo) + +-config MATOM +- bool "Intel Atom" ++ Enables -march=core2 ++ ++config MNEHALEM ++ bool "Intel Nehalem" ++ select X86_P6_NOP + ---help--- + +- Select this for the Intel Atom platform. Intel Atom CPUs have an +- in-order pipelining architecture and thus can benefit from +- accordingly optimized code. Use a recent GCC with specific Atom +- support in order to fully benefit from selecting this option. ++ Select this for 1st Gen Core processors in the Nehalem family. ++ ++ Enables -march=nehalem ++ ++config MWESTMERE ++ bool "Intel Westmere" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for the Intel Westmere formerly Nehalem-C family. ++ ++ Enables -march=westmere ++ ++config MSILVERMONT ++ bool "Intel Silvermont" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for the Intel Silvermont platform. ++ ++ Enables -march=silvermont ++ ++config MSANDYBRIDGE ++ bool "Intel Sandy Bridge" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for 2nd Gen Core processors in the Sandy Bridge family. ++ ++ Enables -march=sandybridge ++ ++config MIVYBRIDGE ++ bool "Intel Ivy Bridge" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for 3rd Gen Core processors in the Ivy Bridge family. ++ ++ Enables -march=ivybridge ++ ++config MHASWELL ++ bool "Intel Haswell" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for 4th Gen Core processors in the Haswell family. ++ ++ Enables -march=haswell ++ ++config MBROADWELL ++ bool "Intel Broadwell" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for 5th Gen Core processors in the Broadwell family. ++ ++ Enables -march=broadwell ++ ++config MSKYLAKE ++ bool "Intel Skylake" ++ select X86_P6_NOP ++ ---help--- ++ ++ Select this for 6th Gen Core processors in the Skylake family. ++ ++ Enables -march=skylake + + config GENERIC_CPU + bool "Generic-x86-64" +@@ -286,6 +434,19 @@ config GENERIC_CPU + Generic x86-64 CPU. + Run equally well on all x86-64 CPUs. + ++config MNATIVE ++ bool "Native optimizations autodetected by GCC" ++ ---help--- ++ ++ GCC 4.2 and above support -march=native, which automatically detects ++ the optimum settings to use based on your processor. -march=native ++ also detects and applies additional settings beyond -march specific ++ to your CPU, (eg. -msse4). Unless you have a specific reason not to ++ (e.g. distcc cross-compiling), you should probably be using ++ -march=native rather than anything listed below. ++ ++ Enables -march=native ++ + endchoice + + config X86_GENERIC +@@ -310,7 +471,7 @@ config X86_INTERNODE_CACHE_SHIFT + config X86_L1_CACHE_SHIFT + int + default "7" if MPENTIUM4 || MPSC +- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU ++ default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU + default "4" if MELAN || M486 || MGEODEGX1 + default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX + +@@ -341,45 +502,46 @@ config X86_ALIGNMENT_16 + + config X86_INTEL_USERCOPY + def_bool y +- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 ++ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MNATIVE + + config X86_USE_PPRO_CHECKSUM + def_bool y +- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM ++ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MATOM || MNATIVE + + config X86_USE_3DNOW + def_bool y + depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML + +-# +-# P6_NOPs are a relatively minor optimization that require a family >= +-# 6 processor, except that it is broken on certain VIA chips. +-# Furthermore, AMD chips prefer a totally different sequence of NOPs +-# (which work on all CPUs). In addition, it looks like Virtual PC +-# does not understand them. +-# +-# As a result, disallow these if we're not compiling for X86_64 (these +-# NOPs do work on all x86-64 capable chips); the list of processors in +-# the right-hand clause are the cores that benefit from this optimization. +-# + config X86_P6_NOP +- def_bool y +- depends on X86_64 +- depends on (MCORE2 || MPENTIUM4 || MPSC) ++ default n ++ bool "Support for P6_NOPs on Intel chips" ++ depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MNATIVE) ++ ---help--- ++ P6_NOPs are a relatively minor optimization that require a family >= ++ 6 processor, except that it is broken on certain VIA chips. ++ Furthermore, AMD chips prefer a totally different sequence of NOPs ++ (which work on all CPUs). In addition, it looks like Virtual PC ++ does not understand them. ++ ++ As a result, disallow these if we're not compiling for X86_64 (these ++ NOPs do work on all x86-64 capable chips); the list of processors in ++ the right-hand clause are the cores that benefit from this optimization. ++ ++ Say Y if you have Intel CPU newer than Pentium Pro, N otherwise. + + config X86_TSC + def_bool y +- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 ++ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MNATIVE || MATOM) || X86_64 + + config X86_CMPXCHG64 + def_bool y +- depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM ++ depends on X86_PAE || X86_64 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM || MNATIVE + + # this should be set for all -march=.. options where the compiler + # generates cmov. + config X86_CMOV + def_bool y +- depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) ++ depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX) + + config X86_MINIMUM_CPU_FAMILY + int +--- a/arch/x86/Makefile 2017-08-02 11:41:47.443200463 -0400 ++++ b/arch/x86/Makefile 2017-08-02 12:14:46.373727353 -0400 +@@ -121,13 +121,40 @@ else + KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup) + + # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) ++ cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) + cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) ++ cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8) ++ cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10) ++ cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona) ++ cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1) ++ cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2) ++ cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1) ++ cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2) ++ cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3) ++ cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4) ++ cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1) + cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona) + + cflags-$(CONFIG_MCORE2) += \ +- $(call cc-option,-march=core2,$(call cc-option,-mtune=generic)) +- cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \ +- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) ++ $(call cc-option,-march=core2,$(call cc-option,-mtune=core2)) ++ cflags-$(CONFIG_MNEHALEM) += \ ++ $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem)) ++ cflags-$(CONFIG_MWESTMERE) += \ ++ $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere)) ++ cflags-$(CONFIG_MSILVERMONT) += \ ++ $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont)) ++ cflags-$(CONFIG_MSANDYBRIDGE) += \ ++ $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge)) ++ cflags-$(CONFIG_MIVYBRIDGE) += \ ++ $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge)) ++ cflags-$(CONFIG_MHASWELL) += \ ++ $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell)) ++ cflags-$(CONFIG_MBROADWELL) += \ ++ $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell)) ++ cflags-$(CONFIG_MSKYLAKE) += \ ++ $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake)) ++ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \ ++ $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic)) + cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic) + KBUILD_CFLAGS += $(cflags-y) + +--- a/arch/x86/Makefile_32.cpu 2017-08-02 11:41:47.444200464 -0400 ++++ b/arch/x86/Makefile_32.cpu 2017-08-02 12:23:41.636760695 -0400 +@@ -22,7 +22,18 @@ cflags-$(CONFIG_MK6) += -march=k6 + # Please note, that patches that add -march=athlon-xp and friends are pointless. + # They make zero difference whatsosever to performance at this time. + cflags-$(CONFIG_MK7) += -march=athlon ++cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native) + cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon) ++cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon) ++cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon) ++cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon) ++cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon) ++cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon) ++cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon) ++cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon) ++cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon) ++cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon) ++cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon) + cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0 + cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0 + cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586) +@@ -31,9 +42,12 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc- + cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686) + cflags-$(CONFIG_MVIAC7) += -march=i686 + cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2) +-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \ +- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) +- ++cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem) ++cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere) ++cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont) ++cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge) ++cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge) ++cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell) + # AMD Elan support + cflags-$(CONFIG_MELAN) += -march=i486 +
