Kévin Redon has uploaded this change for review. ( https://gerrit.osmocom.org/12809
Change subject: add 20 MHz clock output ...................................................................... add 20 MHz clock output use GCLK5 to output 20 MHz clock on PA11/GCLK_IO[5] for SIM cards clock. this can be further divided by the NCN8025 before reaching the SIM. Change-Id: I2c0d6a31ec63a87e04ef4e3afbedce3a221324cc --- M sysmoOCTSIM/atmel_start_config.atstart M sysmoOCTSIM/config/hpl_gclk_config.h 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/09/12809/1 diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 09c0b2d..5c7cc2c 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -648,7 +648,7 @@ enable_gclk_gen_2: true enable_gclk_gen_3: true enable_gclk_gen_4: false - enable_gclk_gen_5: false + enable_gclk_gen_5: true enable_gclk_gen_6: false enable_gclk_gen_7: false enable_gclk_gen_8: false @@ -688,9 +688,9 @@ gclk_arch_gen_4_oe: false gclk_arch_gen_4_oov: false gclk_arch_gen_4_runstdby: false - gclk_arch_gen_5_enable: false + gclk_arch_gen_5_enable: true gclk_arch_gen_5_idc: false - gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oe: true gclk_arch_gen_5_oov: false gclk_arch_gen_5_runstdby: false gclk_arch_gen_6_enable: false @@ -734,9 +734,9 @@ gclk_gen_4_div: 1 gclk_gen_4_div_sel: false gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_5_div: 1 + gclk_gen_5_div: 5 gclk_gen_5_div_sel: false - gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_oscillator: Digital Phase Locked Loop (DPLL1) gclk_gen_6_div: 1 gclk_gen_6_div_sel: false gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h index d16af6f..6b7586c 100644 --- a/sysmoOCTSIM/config/hpl_gclk_config.h +++ b/sysmoOCTSIM/config/hpl_gclk_config.h @@ -387,7 +387,7 @@ // <i> Indicates whether generic clock 5 configuration is enabled or not // <id> enable_gclk_gen_5 #ifndef CONF_GCLK_GENERATOR_5_CONFIG -#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#define CONF_GCLK_GENERATOR_5_CONFIG 1 #endif // <h> Generic Clock Generator Control @@ -404,7 +404,7 @@ // <i> This defines the clock source for generic clock generator 5 // <id> gclk_gen_5_oscillator #ifndef CONF_GCLK_GEN_5_SOURCE -#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DPLL1 #endif // <q> Run in Standby @@ -425,7 +425,7 @@ // <i> Indicates whether Output Enable is enabled or not // <id> gclk_arch_gen_5_oe #ifndef CONF_GCLK_GEN_5_OE -#define CONF_GCLK_GEN_5_OE 0 +#define CONF_GCLK_GEN_5_OE 1 #endif // <q> Output Off Value @@ -446,7 +446,7 @@ // <i> Indicates whether Generic Clock Generator Enable is enabled or not // <id> gclk_arch_gen_5_enable #ifndef CONF_GCLK_GEN_5_GENEN -#define CONF_GCLK_GEN_5_GENEN 0 +#define CONF_GCLK_GEN_5_GENEN 1 #endif // </h> @@ -454,7 +454,7 @@ //<o> Generic clock generator 5 division <0x0000-0xFFFF> // <id> gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV -#define CONF_GCLK_GEN_5_DIV 1 +#define CONF_GCLK_GEN_5_DIV 5 #endif // </h> // </e> -- To view, visit https://gerrit.osmocom.org/12809 To unsubscribe, or for help writing mail filters, visit https://gerrit.osmocom.org/settings Gerrit-Project: osmo-ccid-firmware Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c0d6a31ec63a87e04ef4e3afbedce3a221324cc Gerrit-Change-Number: 12809 Gerrit-PatchSet: 1 Gerrit-Owner: Kévin Redon <kre...@sysmocom.de>