Selon Ivan Curtis <[EMAIL PROTECTED]>:

> I have run into an issue with ghdl which I believe is a bug. I have
> included a small example called bug.vhdl to illustrate the problem.
>
> When the code is analysed, I get the following error message:
>
> orion % ghdl -a bug.vhd
> bug.vhd:18:16: object subtype is not locally static
> ghdl: compilation error
>
> If the port addr is defined with a fixed range, the analysis is
> OK. But since the value of the generic is fixed at elaboration time, I
> think the sub range addr(1 downto 0) is in fact locally static. VHDL
> simili compiles and elaborates OK.
Hi,

Sorry for the late reply, but I was travelling.

Here is my analysis:
according to LRM 8.8:
"
If the expression is of a one-dimensional character array type, then the
expression must be one of the following:

1)      -- The name of an object whose subtype is locally static

2)      -- A slice name whose prefix is one of the members of this list and
whose discrete range is a locally static discrete range
"

Your slice is correct accoring to 2) since the range is a locally discrete
range.  However the slice prefix is not correct according to 1) since its
subtype is not locally static.  Therefore, the slice should be rejected.
So GHDL is correct according to LRM.

For sure, these rules are somewhat stupid but these are the rules :-(
You could try with an alias or a qualified expression.

Tristan.


>
> At the moment I am working-around by assigning to a local signal which
> has fixed range.
>
> Best regards,
> Ivan
>
> -- bug.vhd included below
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity bug is
>   generic (ADDR_SIZE : natural := 4
>   );
>   port (clk : in std_logic;
>         addr : in std_logic_vector(ADDR_SIZE - 1 downto 0);
>         data : out std_logic_vector(3 downto 0)
>   );
> end bug;
>
> architecture expose of bug is
> begin
>   p1: process (clk)
>   begin
>     if clk'event and clk = '1' then
>       case addr(1 downto 0) is
>         when "00"   => data <= "0000";
>         when others => data <= "1111";
>       end case;
>     end if;
>   end process p1;
> end architecture expose;

Reply via email to