Hello,
I have tried to simulate a fifo which synthesizes to srls with Xilinx xst.
Unfortunately this does not seem to work correctly with my ghdl version,
on a x86_64:
GHDL 0.26 (20070408) [Sokcho edition]
Compiled with GNAT Version: 4.1.2
GCC back-end code generator
Written by Tristan Gingold.
Whenever I try to write a value into the fifo memory(0) becomes "eveUUUUU".
As far as I know 'e' and 'v' are not valid for std_logic.
Any help is appreciated,
Mark.
--------------------------------------- The fifo model
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vector_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity sync_fifo is
generic(
g_depth: integer:=16; -- The number of words to be stored in the fifo
g_width: integer:=8; -- The width of the input and output data
g_room: integer:=5 -- The number of empty words for "almost_full"
);
port(
clock: in std_logic;
reset: in std_logic;
we: in std_logic;
din: in std_logic_vector(g_width-1 downto 0);
almost_full: out std_logic;
rd: in std_logic;
dout: out std_logic_vector(g_width-1 downto 0);
empty: out std_logic
);
end sync_fifo;
architecture infer_srl of sync_fifo is
signal a: integer range 0 to g_depth;
type memory_v is array(integer range<>) of std_logic_vector(g_width-1 downto 0);
signal memory: memory_v(0 to g_depth):=(others=>(others=>'0'));
begin
almost_full<=to_std_logic(g_depth-a<g_room);
process(clock)
begin
if clock'event and clock='1' then
if reset='1' then
a<=0;
else
empty<=to_std_logic(a=0);
if we='1' then
memory<=din & memory(0 to g_depth-1);
end if;
if we='0' and rd='1' and a>0 then
a<=a-1;
elsif we='1' and rd='0' and a/=g_depth then
a<=a+1;
end if;
end if;
end if;
end process;
dout<=memory(a);
end;
--------------------------------------- The test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_sync_fifo is
end;
architecture first of test_sync_fifo is
signal clock: std_logic:='0';
signal reset: std_logic:='1';
signal we: std_logic:='0';
signal din: std_logic_vector(7 downto 0):=(others=>'0');
signal almost_full: std_logic;
signal rd: std_logic:='0';
signal dout: unsigned(7 downto 0);
signal empty: std_logic;
begin
clock<=not clock after 10 ns;
reset<='0' after 30 ns;
dut: entity work.sync_fifo generic map (
g_depth=>16,
g_width=>8,
g_room=>5
) port map (
clock=>clock,
reset=>reset,
we=>we,
din=>din,
almost_full=>almost_full,
rd=>rd,
unsigned(dout)=>dout,
empty=>empty
);
process
begin
wait for 1 us;
loop
wait until rising_edge(clock);
we<='1';
din<=std_logic_vector(unsigned(din)+1);
wait until rising_edge(clock);
we<='0';
end loop;
end process;
end;
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