On Tue, Jun 3, 2008 at 12:21 PM, Wesley J. Landaker <[EMAIL PROTECTED]> wrote:
> On Tuesday 03 June 2008 10:04:24 Pascal Giard wrote:
>> On Tue, Jun 3, 2008 at 11:53 AM, Wesley J. Landaker <[EMAIL PROTECTED]>
>> wrote: [...]
>>
>> > and many custom "synthesis" tools for abstract langauges "compile" to
>> > VHDL.
>>
>> FWIW, with Forté Cynthesizer in mind, or to Verilog...
>
> I've actually toyed with this idea for some time (but will realistically
> probably never have time to implement it):
>
>  1) Modify GHDL to compile to LLVM.
>  2) Modify Icarus Verilog to compile to LLVM.
>  3) Create a "VHDL" LLVM backend target.
>  4) Create a "Verilog" LLVM backend target.
>
> Then you could actually compile VHDL into Verilog and vice-versa (and do
> other crazy things with other languages and targets). Of course, its
> only "simple" in theory, LLVM isn't a great parallel IIR, etc, etc. But,
> hey, it's a good dream. Maybe someday. ;)

It's not an easy job... Following comments i've given them, talking
with the guys of Forté (at DVCon08), they told me how of a hard time
they have generating good Verilog from SystemC models.

My comments were about a implementation comparison i made for a Master
class were I've compared generated Verilog from a SystemC model with a
hand-written VHDL model. It came with no surprise that my hand-written
VHDL was much more efficient¹ but i was expecting it to be closer. For
what it's worth they've told me that they've improved code generation
for the upcoming release but i haven't taken the time to test.

Anyway, before going to much out of scope... I'd be interested in the
first proposal... But i don't have much time to dedicate to it so i
can't "lead" that project either. I'd gladly contribute tho.

-Pascal
¹ 2 times less space, 4 times faster.
-- 
Homepage (http://organact.mine.nu)
Debian GNU/Linux (http://www.debian.org)
LACIME: École de technologie supérieure (http://lacime.etsmtl.ca)

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