Joyeuse Noel Tristan,
        Voici un snippet attache qui montre l'error, c'est tout.  Bien a vous
Ian.
ghdl version
GHDL 0.26 (20070408) [Sokcho edition]
 Compiled with GNAT Version: 4.2.3 20071019 (prerelease)
 GCC back-end code generator
from Ubuntu repository.



On Fri, 2008-12-26 at 03:46 +0100, Tristan Gingold wrote:
> On Fri, Dec 19, 2008 at 08:21:40PM -0500, Ian Chapman wrote:
> > Hi, I think this is something to do with the newer standards.  Shift
> > srl, sll, rol and ror assemble in ghdl.  sla and sra return
> > 
> > "no function declarations for operator "sra"
> > /usr/lib/ghdl/bin/ghdl: compilation error" 
> > 
> > is there a work round or should I live with it?  Thanks in advance.
> 
> Can you provide a reproducer ?  It really depends on the profile.
> 
> Tristan.
> 
> _______________________________________________
> Ghdl-discuss mailing list
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------------------------------------------------------------------
---
---  Shift_reg.vhd
---  
---  18 December 2008 Ian Chapman
---  Purpose to test my VHLD skills
---
------------------------------------------------------------------

library IEEE;			--Use standard IEEE libs as recommended by Tristan.
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity Shift_reg is

Port (
	clock: in std_logic;
	reset : in std_logic;
	data: out unsigned(7 downto 0);
	cmd: in std_logic_vector(3 downto 0)
    );
end Shift_reg;

architecture Shift_reg_architecture of Shift_reg is


	------------------------------------------------------------------------
	-- Signal Declarations
	------------------------------------------------------------------------

signal reg_a : unsigned (7 downto 0);


begin	--architecture

shift :process (clock, cmd)
begin

if reset = '1' then
	reg_a <= x"00";
	elsif rising_edge(clock) then
	Case cmd is

		when x"0" =>			--ROR okay			
			reg_a <= reg_a ror 1;
			reg_a(0) <= '0';
			
		when x"1" =>			--ROL okay
			reg_a <= reg_a rol 1;
			

		when x"2" =>			--SRL okay
			reg_a <= reg_a srl 1;
			

		when x"3" =>			--SLL okay
			reg_a <= reg_a sll 1;
			

		when x"4" =>			--SRA fail
			reg_a <= reg_a sra 1;
			
		when others =>
			reg_a <= reg_a sla 1;	--SLA fail

--shift_reg.vhd:61:39: no function declarations for operator "sra"
--shift_reg.vhd:64:39: no function declarations for operator "sla"

	end case;
end if;

end process;

end Shift_reg_architecture;

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