Paulo Costa a écrit : > Unfortunaly, I really can't afford an FPGA. Not even a "cheap" one. ok. However, maybe you could be interested to have a look (for the future) at Armadeus project in France : http://www.armadeus.com/wiki/index.php?title=Main_Page On the same board, you get a FPGA (Spartan) and a ARM processor, running Linux. > Even though I know an FPGA is completely different from a CPU, I was > planning to use it for some quite silly things, and if I could run > them as a simulation, that would probably be acceptable. I personally find your idea interesting ! Replacing SW blocks by HW accelerators is common, but the opposite is quite rare ! But it represents much much work I think with poor performances at the end, if you directly embedd an event-driven VHDL simulator. Keep us informed !
Note that it is not so far from what the community of so-called "synchronous languages" (used in aeronautics) tend to do, with a different approach : from specification captured in dedicated languages inspired by synchronous circuits (hence their names), their compilers are capable of generating mono-threaded embedded C code (plus some formally proofs on some properties). The idea is to statically find the correct ordering between "components", in order to remove the scheduler. Maybe you have already heard about Esterel or Lustre...If you are interested, you can have a look at http://www.irisa.fr/distribcom/benveniste/pub/synch_ProcIEEE_2002.pdf Happy new year to GHDL list ! Jean-Christophe _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
