Jun 16, 2009 12:57:27 AM, ghdl-discuss@gna.org wrote:
I'm having trouble doing a hierarchical project using GHDL. I have a
entity called mmc1, which I'd like to contain a instance of a
"shift_reg". It seems to work OK if all the inputs of the sub-entity
are explicit internal signals, but passing along inputs from the top
level to the bottom level entity fails. Here is what I'm seeing:
$ ghdl -a mmc1.vhdl
mmc1.vhdl:44:31: no interface for 'clk' in association
/usr/lib/ghdl/bin/ghdl: compilation error
Any idea what I'm doing wrong here? From the examples I'm learning
VHDL from (Altera), I don't see anything wrong with this. It has the
same complaint about "data_in" if I assign it to cpu_d0 instead of
test2. Thanks for any suggestions,
Chris
library IEEE;
use IEEE.Std_logic_1164.all;
entity mmc1 is
generic (
hw_version : string := "MMC1"
);
port (
cpu_d0 : in bit; -- D0 data line from CPU
cpu_d7 : in bit; -- D7 data line from CPU
m2 : in bit -- the M2 or Phi2 input clock
);
end mmc1;
architecture arch of mmc1 is
component shift_reg
port (
data_in : in STD_LOGIC; -- input data
clk : in STD_LOGIC;
reset : in STD_LOGIC; -- synchronous reset
data_out : out std_logic_vector
);
end component;
signal test : std_logic_vector(1 downto 0) := "00";
signal test2 : std_logic := '0';
begin -- arch
input_shift_reg : entity work.shift_reg
generic map (width=>2, shift_dir_right=>true,
sense_rising_edge=>true, reset_active_high=>true )
port map (data_in=>test2, clk=>m2, reset => cpu_d7, data_out => test);
end architecture arch;
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