Hi,
I have been experimenting with using GHDL to simulate a processor
design. The good news is that GHDL did compile and simulate the design
so that a comprehensive test ran to completion and produced the same
result. Small changes to the VHDL were required, but these appeared to
be moving closer to the VHDL standard. These were:
* Some declarations of std_logic_vector constants were found with
implicit dimensions. These needed to be given dimensions.
< constant VALID0 : std_logic_vector := "10";
---
> constant VALID0 : std_logic_vector (1 downto 0) := "10";
* Some uses of the mod operator were ambiguous as to the
interpretation of the type of the operands, which required a cast.
< case value'length mod 4 is
---
> case integer'(value'length) mod 4 is
* One of the text files which is read the simulation required
hexadecimal values to be padded with zeros to a multiple of four digits
to be read successfully by the procedure "hread".
Some statistics:
Active lines of code (excluding lines with only comments or
whitespace) 186210
Final executable size
34 Mbytes
Memory requirement when running
484 Mbytes
The bad news is that the simulation took two hours, whereas on a
proprietary simulator it completes in around three minutes. My question
is, would it be possible to speed it up, assuming that significant
resource was available? Would there be interest in doing this? If it was
less than five times slower than the proprietary simulator, it would be
cost effective to buy five times the computers in order to use GHDL and
save on simulator licenses.
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