Hello,
I'm trying to use in Win32 environment the ghdl compiler.
I tryed to compile the attached files with:
*ghdl -a --ieee=synopsys --workdir=work
C:\USERS\MySP\rtl\MySP_pkg.vhd C:\USERS\MySP\rtl\MySP_PMEM.vhd*
Then running the command:
*ghdl -m --workdir=work mysp_pmem*
I got the following message:
*ghdl: cannot load entity "mysp_pmem"*
but if I run:
* ghdl -d --workdir=work
*I got:*
** package mysp_pkg
entity mysp_pmem
architecture rtl of mysp_pmem
*so I don't understand the message, everything seems into work directory.
The same rtl compile well on cadence ncvhdl.
Could someone help me?
Best regards
Luca
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
package MySP_pkg is
constant IDATAS : integer := 24; -- Input data length
constant ODATAS : integer := 24; -- Output data length
constant XDATAS : integer := 32; -- Xmem data length
constant XADDRS : integer := 10; -- Xmem address length
constant YDATAS : integer := 32; -- Ymem data length
constant YADDRS : integer := 10; -- Ymem address length
constant FDATAS : integer := 30; -- Fmem data length
constant FADDRS : integer := 10; -- Fmem address length
constant MDATAS : integer := 57; -- Truncated multiplication size
constant ADATAS : integer := 57; -- Accumulator size
constant IFSize : integer := 6; -- Instruction
field Size
constant ISize : integer := 32; -- Instruction
Size
constant PADDRS : integer := 10; -- Program
Memory addr. length
-----------------------------------------------------------------------------
-- Instruction Set --
-----------------------------------------------------------------------------
constant nop : std_logic_vector(ISize-1 downto 0) := (others => '0');
constant macxy : std_logic_vector(IFSize-1 downto 0) := "000001";
constant mulxy : std_logic_vector(IFSize-1 downto 0) := "000010";
end MySP_pkg;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library work;
use work.MySP_pkg.all;
entity MySP_PMEM is
generic (
WBIT : integer := 32; -- Word lenght
ABIT : integer := 10); -- Addres length
port (
mck : in std_logic; -- system clock
dout : out std_logic_vector(WBIT-1 downto 0);
add : in std_logic_vector(ABIT-1 downto 0)
);
end MySP_PMEM;
architecture rtl of MySP_PMEM is
SUBTYPE MType IS std_logic_vector(dout'RANGE);
TYPE MemType IS ARRAY (0 TO (2**ABIT)-1) OF MType;
constant Contents : MemType:=(0 => nop,
1 => mulxy & conv_std_logic_vector(5,13) &
conv_std_logic_vector(23,13),
2 => macxy & conv_std_logic_vector(31,13) &
conv_std_logic_vector(7,13),
others => (others => '0')
);
begin -- rtl
p_out: process (mck)
begin -- process p_out
if mck'event and mck = '1' then -- rising clock edge
dout <= Contents(conv_integer(unsigned(add)));
end if;
end process p_out;
end rtl;
_______________________________________________
Ghdl-discuss mailing list
[email protected]
https://mail.gna.org/listinfo/ghdl-discuss
