I have defined in a package two arraytype. (one for in and on for out). Now I can use this new type for definition also in port declaration. GHDL has also no problem with it, all command running.
But I can not see this array in GTKwave? Why not? This should become a 1D-DCT. Best regard Rene Doss
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:28:56 10/27/2009
-- Design Name:
-- Module Name: cdt - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.numeric_std.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use work.my_package.all;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dct is
port(
clk: std_logic;
data_in:in vector_char;
data_out: out vector_word;
calc : in std_logic);
end dct;
architecture Behavioral of dct is
signal c_in: vector_char;
signal a:vector_word;
signal counter: integer;
begin
c_in<=data_in;
data_out<=a;
process (clk)
variable temp: signed (15 downto 0);
variable m_a: signed (7 downto 0);
variable m_b:integer;
begin
if clk'event and clk='1' then
temp:= m_a*m_b;
case (counter) is
when 1 => m_a:= c_in(0); m_b:=90;
---
when 2 => m_a:= c_in(1);m_b:=125;
a(0)<=temp; a(1)<=temp;a(2)<=temp;a(3)<=temp;
a(4)<=temp; a(5)<=temp;a(6)<=temp;a(7)<=temp;
when 3 => m_a := c_in(1); m_b:=106;
a(0)<=a(1)+temp; a(7)<=a(7)-temp;
when 4 => m_a :=c_in(1);m_b:=71;
a(1)<=a(1)+temp; a(6)<=a(6)-temp;
when 5 => m_a :=c_in(1);m_b:=25;
a(2)<=a(2)+temp; a(5)<=a(5)-temp;
----
when 6 => m_a:=c_in(2);m_b:=117;
a(3)<=a(3)+temp; a(4)<=a(4)+temp;
when 7 => m_a:=c_in(2);m_b:=49;
a(0)<=a(0)+temp;a(3)<=a(3)-temp;
a(4)<=a(4)-temp;a(5)<=a(7)+temp;
---
when 8=> m_a:=c_in(3);m_b:=106;
a(1)<=a(1)+temp; a(2)<=a(2)-temp;
a(5)<=a(5)-temp; a(6)<=a(6)+temp;
when 9=> m_a:=c_in(3);m_b:=25;
a(0)<=a(0)+temp; a(7)<=(7)-temp;
when 10=> m_a:=c_in(3);m_b:=125;
a(1)<=a(2)-temp; a(6)<=a(6)+temp;
when 11=> m_a:=c_in(3);m_b:=71;
a(2)<=a(2)-125; a(5)<=a(5)+temp;
--
when 12=> m_a:=c_in(4);m_b:=90;
a(3)<=a(3)-temp; a(3)<=a(3)+temp;
--
when 13=> m_a:=c_in(5);m_b:=71;
a(0)<=a(0)+temp; a(1)<=a(1)-temp;
a(2)<=a(2)-temp; a(3)<=a(3)+temp;
a(4)<=a(4)+temp; a(5)<=a(5)+temp;
a(6)<=a(6)-temp; a(7)<=a(7)+temp;
when 14=> m_a:=c_in(5);m_b:=125;
a(0)<=a(0)+temp; a(7)<=a(7)-temp;
when 15=> m_a:=c_in(5);m_b:=25;
a(1)<=a(1)-temp; a(6)<=a(6)+temp;
when 16=> m_a:=c_in(5);m_b:=106;
a(2)<=a(2)+temp; a(6)<=a(6)-temp;
--
when 17=> m_a:=c_in(6);m_b:=49;
a(3)<=a(3)+temp; a(4)<=a(4)-temp;
when 18 => m_a:=c_in(6);m_b:=117;
a(0)<=a(0)+temp; a(7)<=a(7)+temp;
a(3)<=a(3)-temp; a(4)<=a(4)-temp;
--
when 19 => m_a:=c_in(7);m_b:=25;
a(1)<=a(1)-temp; a(2)<=a(2)+temp;
a(5)<=a(5)+temp; a(6)<=a(6)-temp;
when 20 => m_a:=c_in(7);m_b:=71;
a(0)<=a(0)+temp; a(7)<=a(7)-temp;
when 21 => m_a:=c_in(7);m_b:=106;
a(1)<=a(1)-temp; a(6)<=a(6)+temp;
when 22 => m_a:=c_in(7);m_b:=125;
a(2)<=a(2)+temp; a(5)<=a(5)-temp;
when 23 => a(3)<=a(3)-temp; a(4)<=a(4)+temp;
when others => temp:=temp ;
end case;
end if;
end process;
process (clk)
begin
if clk'event and clk='1' then
if calc='1' then
counter<=counter+1;
else
counter<=0;
end if;
end if;
end process;
end Behavioral;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:47:23 10/29/2009
-- Design Name:
-- Module Name: /home/red/fpga/VHDL/dct_1/dct_tb.vhd
-- Project Name: dct_1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cdt
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the
post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.my_package.all;
ENTITY dct_tb IS
END dct_tb;
ARCHITECTURE behavior OF dct_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dct
port(
clk: std_logic;
data_in:in vector_char;
data_out: out vector_word;
calc : in std_logic);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal data_in : vector_char;
signal calc : std_logic := '0';
--Outputs
signal data_out : vector_word;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dct PORT MAP (
clk => clk,
data_in => data_in,
data_out => data_out,
calc => calc
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process
begin
calc<='0';
wait for 5 ns;
data_in(0)<="00000111";
data_in(1)<="00000111";
data_in(2)<="00000111";
data_in(3)<="00000111";
data_in(4)<="00000111";
data_in(5)<="00000111";
data_in(6)<="00000111";
data_in(7)<="00000111";
wait for 20 ns;
calc<='1';
wait for 400 ns;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100 ms;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
run.sh
Description: application/shellscript
-- Package File Template -- -- Purpose: This package defines supplemental types, subtypes, -- constants, and functions library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; package my_package is type vector_char is array (0 to 7) of signed (7 downto 0); type vector_word is array (0 to 7) of signed (15 downto 0); end my_package; package body my_package is end my_package;
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