Hi Martin, Your rst signal has no effect!!
Put a clk signal in your design. Use a second signal write enable as static signal too control your output. entity .... port( clk : in std_logic; write_en: in std_logic; .... ); write_words:process( clk) file out_file : text open write_mode is filename; variable out_line : line; variable out_data : integer; begin if clk'event and clk='1' then if write_en='1' then write operations...... end if; ... end if; end process; René Doß Am Samstag, den 30.01.2010, 18:19 +0100 schrieb Martin Zenzes: > integer'image _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
