Hello, I know that Tristan Gingold has thought about this, and tonight I can't get my ideas straight... So I was thinking about how to make a good VHDL synthesizer with minimal effort (compared to the complexity of commercial ones) and I think that I have found how to do this. Please excuse me if I get something wrong or if I re-invent the wheel, the car and the road...
Let's start with GHDL : it does not need to be deeply modified. What we need is some way to convert valid VHDL to EDIF, and GHDL converts VHDL to executable code. My idea is to create a virtual/pseudo-CPU architecture (a bit like Java) that GCC will easily target. There can be infinite registers, unconstrained memory etc because the CPU is not a real one. The output does not even need to be assembled into binary code. The output text then goes to a pseudo-simulator that will perform the elaboration. Then the instructions can be flagged and converted one by one to EDIF gates. Other existing free SW can then take the netlist and perform boolean reductions before giving the result to P&R. I know that it can't be so simple in practice, what I describe amounts to the work done by GHDL's GRT (at least). However, I wonder if the idea of a pseudo-CPU has ever been published somewhere. IMHO it is not very invasive to the existing code and it will benefit from today's good VHDL coverage with the least effort. Boolean reduction is another subject which is well described in the academic and professional papers, so i'll leave it to others. What is missing now is a bridge from GCC to EDIF, right ? Please tell me what is worth and what is wrong in this post. happy sunday, yg -- http://ygdes.com / http://yasep.org _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
