On 29/07/10 9:45 AM, Yann GUIDON wrote: > Le mer 28/07/10 23:18 , Felipe Balbi a écrit:: >> Hi all, > >> How can I create a library out of a design to be re-used by other >> designs ? Is it so that I just have to analyze the design and put >> it under /usr/lib/gcc/i686-pc-linux-gnu/4.3.4/vhdl/lib// ?? > no :-) > > maybe you mistake "package" and "library". VHDL uses "packages". > you should know this : > http://www.effectgames.com/demos/canvascycle/?sound=0 > (i just googled it) > > you can make VHDL packages ("libraries") very easily and they are often > in the same directory. There are more sophisticated possibilities > but you can start by compiling your .vhdl file containing the shared code. > By default the output goes to the current directory and your > architectures can use it with the "work" access path : >
IEEE 1076-1993 Annex B Glossary B.142 library: See design library. B.68 design library: A host-dependent storage facility for intermediate-form representations of analyzed design units. (§ 11.2 ) 11.2 Design libraries ... There are two classes of design libraries: working libraries and resource libraries. A working library is the library into which the library unit resulting from the analysis of a design unit is placed. A resource library is a library containing library units that are referenced within the design unit being analyzed. Only one library may be the working library during the analysis of any given design unit; in contrast, any number of libraries (including the working library itself) may be resource libraries during such an analysis. --------- There is no distinction as to content (no implication that a library is only package declarations, package bodies and associated global declarations). This is what the --work flag is for ghdl, that you can store analyzed code in different named design libraries. If one were to imagine a gate level design implementation in VHDL, the use of configuration declarations and multiple target 'technology gate level libraries', you would discern one use of design libraries. You can have standard gate level constructs named identically and target implementation in a different vendor implementation readily. The use of multiple design libraries allows you to keep your 'intermediate-form representations available without the consequences of name space collision by say re-analyzing 'DFF' into your working library, the 'new' version overwriting the original. When you use the same named entities found in multiple design libraries the distinction between one and another is by selected names containing the design library names. You in effect forward carry the elaborated name into the analysis process. Contrast this with say 'C', where you use compile time association (re-analysis) and compiler flags to associate the correct library when the potential for a name collision exists. Unique handling is provided in VHDL by configuration declarations and selected names. - IEEE1076-1993: 2.6 Package bodies A package body defines the bodies of subprograms and the values of deferred constants declared in the interface to the package. ---------- You can think of a package as analogous to an include file continuing the 'C' analogy. A major difference in VHDL is that you use the intermediate-form representation (it's been analyzed). - IEEE-1076-1993: Section 2 Subprograms and packages Subprograms define algorithms for computing values or exhibiting behavior. They may be used as computational resources to convert between values of different types, to define the resolution of output values driving a common signal, or to define portions of a process. Packages provide a means of defining these and other resources in a way that allows different design units to share the same declarations. There are two forms of subprograms: procedures and functions. A procedure call is a statement; a function call is an expression and returns a value. Certain functions, designated pure functions, return the same value each time they are called with the same values as actual parameters; the remainder,impure functions, may return a different value each time they are called, even when multiple calls have the same actual parameter values. In addition, impure functions can update objects outside of their scope and can access a broader class of values than can pure functions. The definition of a subprogram can be given in two parts: a subprogram declaration defining its calling conventions, and a subprogram body defining its execution. Packages may also be defined in two parts. A package declaration defines the visible contents of a package; a package body provides hidden details. In particular, a package body contains the bodies of any subprograms declared in the package declaration. --------- The major distinction between using subprograms and components is that you cannot determine internal state of subprograms during execution of the elaborated model. You can also not test timing. It's possible to use subprograms in such away you can't meet your timing goals for the design model. Subprograms count entirely on synthesis tools to produce a model working within time constraints and only contain sequential statements. The designer trades off faster abstract model execution for poor visibility and greater synthesis effort which can involve the loop through to re-writing or devolving subprograms to meet timing goals. VHDL wasn't envisioned to contain the majority of a design in subprograms, regardless of the convenience to designers. That they can be successful is a tribute to performance and complexity advances in synthesis tools. That they try is perhaps attributed to viewing VHDL as just another computer language. In defense, I went through the very first Synopsys design compiler class to include VHDL. My first reaction was that VHDL is a wonderful language for describing designs and that no one actually had any business writing in it. (It should be generated by tools, the accuracy required to implement the verbosity is difficult.). Note the bit about different design units sharing the same declarations in the first paragraph quoted from Section 2 above. Back to components: - 4.5 Component declarations A component declaration declares a virtual design entity interface that may be used in a component instantiation statement. A component configuration or a configuration specification can be used to associate a component instance with a design entity that resides in a library. ---------- If you sweep your component declarations into a package you could re-target them based on re-analysis of the package body. In effect two different package bodies, the last one analyzed taking effect. Unfortunate the rules on Order of analysis tell us: 11.4 Order of analysis A given library unit is potentially affected by a change in any library unit whose name is referenced within the given library unit. A secondary unit is potentially affected by a change in its corresponding primary unit. If a library unit is changed (e.g., by reanalysis of the corresponding design unit),then all library units that are potentially affected by such a change become obsolete and must be reanalyzed before they can be used again. ---------- The effect would be to potentially require a lot of packages, to invoke re-analysis of only those actually affected design units. All in all the amount of time taken to analyze design units is usually dwarfed by the editing time to make changes. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
