The component of the IBUFG you have declared in the testbench does not precisely match the IBUFG entity. The ports are std_logic and std_ulogic. I've had some problems in the past with this, causing exactly the behavior you see. Whether it's a GHDL thing or a VHDL thing I don't know.
Regards, Kevin Date: Tue, 30 Nov 2010 22:20:07 +0100 From: [email protected] To: [email protected] Subject: [Ghdl-discuss] Simple line simulation Hallo, I have a problem or a bug or what ever. Now I have reduced to the smallest code. The reproducer is in the attachment. In my code I have a simple connection from input to output. The amazing is the signal output is correct but the signal o in the instance is undefined. The signal o and output are the same but I get different waves??! René _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
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