Le 21/12/2010 18:02, Kevin Steffensen a écrit :
That's not legal VHDL. I'm pretty sure what you mean is this :
entity hello is
end;
architecture bug of hello is
type state_type is (s0,s1);
signal state : state_type;
begin
stim : process
begin
report state_type'image(state);
wait;
end process stim;
end bug;
Hi Kevin
No, I really wanted to print the enumerated value s0 directly.
I believe it is legal, but may be I am wrong.
JCLL
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