On Mon, 14 Feb 2011 20:33:08 +0000, Alex Huntley
<[email protected]> wrote:
Nice work! Sounds really good!
Thank you :-)
I had to go through a lot of objections from people on comp.lang.vhdl
but the need for speed was too strong :-)
Do you still get a significant speedup for std_logic_ vector of
other more arbitrary lengths - e.g. 13 or 17 or 31?
i guess not. I haven't tried but that was one of the issues i imagined.
indeed SHA1 was great because it was designed to be efficient
both with CPU and custom electronics. My next projects will extend
that.
What about vectors longer than 32 bits? Would you still get a
dramatic speed-up on a 32 bit machine?
i haven't measured yet.
For now i create subtypes with the size in the name so special
overloading can take over and smooth out edge cases, but i'm not that
far.
longer vectors won't have much more speedup anyway.
more speedup will come from managing the range-checking code
that is inserted at every array/table access.
a custom pragma would be good ;-)
How does your new source code handle the odd 'U' or 'Z' in amongst
'1' s and '0's?
it does not when you use the integer package.
change the header by including the int_sulv package
and you get support for 'X', 'U', 'Z' etc. (and it get slow
but synthesisable)
remember : this code/extension is only for helping
high-level description code, written in Pascal or C-like syntax, to
work,
before creating new architecture with more precise descriptions.
Simulation speedup is meant to help system-wide evaluation for top-down
design projects, to help get a better picture of the whole before
digging
in the details.
This comes at a cost now because the source code must be "rewritten"
with a very particular, constraining style, because
it's hard to combine the advantages of both integers and sulv.
If more people use and enhance these extensions, however,
that could lead to other breakthroughs :-)
Thanks for your efforts and announcing your discovery! Long LIve
Open Source!
Long live GHDL ! :-)
YG
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