On 18/02/2011 11:25, Christophe Clienti wrote: > I need to access to internal signals of a design under test in a vhdl > testbench. The tested design instanciates multiple entities and I > don't want to change them by adding a port to monitor desired signals. > Is there some possibilities to do that (in vhdl or in a c program) ? > > Christophe > Example:
--probe package: library ieee; use ieee.std_logic_1164.all; package probe is signal probe_example:std_logic; end package; --the design under test: --RTL_SYNTHESIS OFF use work.probe.all; --RTL_SYNTHESIS ON architecture rtl of design_tested is ... begin --RTL_SYNTHESIS OFF probe_example<=signal_to_probe; --RTL_SYNTHESIS ON ... end architecture --somewhere in the test bench: --don't forget to add "use work.probe.all;" ... write_reg(15); --generate some stimuli assert probe_example=15; --check that stimuli changed the value of the signal note : the pragma comments RTL_SYNTHESIS ON/OFF are usefull to not disturb the synthesis tools (standard IEEE 1076.6) note2: VHDL 2008 have a new syntax to do this more easily, but I don't know if it is supported by GHDL _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
