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--- Begin Message ---
Hi All!
I'm trying to run the attached testbench, yes this is a stupid
testbench, is just to show how to use ghdl.
The testbench works as spected on Linux (it injects the 16 values to the
converted).
But when I run the "run.bat" on Windows the testbench hangs forever,
looks like it doesn't advance time.
If I uncomment the report line it works fine ... ???!!??
Any advice?
Regards, Salvador
P.D. I tried all the debug options and none worked
--
_______________________________________________________________
Ing. Salvador Eduardo Tropea http://utic.inti.gob.ar/
INTI-Electrónica e Informática Tel: (+54 11) 4724 6315
Colectora de Av. General Paz 5445 San Martín - B1650KNA
Casilla de Correo 157 FAX: (+54 11) 4754 5194
Buenos Aires * Argentina http://www.inti.gob.ar/
-- 27.06.08 ------------------------------------ Gray2BinN_1
-- CONVERSOR DE CÓDIGO GRAY A BINARIO DE n BITS
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------
entity Gray2Bin_1 is
generic (n: integer := 4); -- por defecto será de 4 bits
port (G : in std_logic_vector (n-1 downto 0);
B : out std_logic_vector (n-1 downto 0));
end entity Gray2Bin_1;
-------------------------------------------------------------
-- DESCRIPCIÓN USANDO LA FUNCIÓN XOR ENTRE VECTORES
architecture bhv1 of Gray2Bin_1 is
signal IB : std_logic_vector (n-1 downto 0);
begin
IB(n-1) <= G(n-1);
IB(n-2 downto 0) <= IB(n-1 downto 1) xor G(n-2 downto 0);
B <= IB;
end architecture bhv1;
-------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Testbench is
end entity Testbench;
architecture Simulador of Testbench is
component Gray2Bin_1 is
generic(
n : integer:=4);
port(
G : in std_logic_vector(n-1 downto 0);
B : out std_logic_vector(n-1 downto 0));
end component Gray2Bin_1;
signal b, g : std_logic_vector(3 downto 0);
begin
DUT : Gray2Bin_1
port map(G => g, B => b);
do_test:
process
begin
-- Simplemente presentar los 16 valores posibles
-- en la entrada
--report "WTF!";
for i in 0 to 15 loop
g <= std_logic_vector(to_unsigned(i,4));
wait for 20 ns;
end loop;
wait;
end process do_test;
end architecture Simulador; -- Entity: Testbench
--- End Message ---
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