On 5/10/2011, at 2:49 AM, Martin Strubel wrote:
I've done done tracing with GDB, it turns out a std_logic_vector has
illegal values (i.e.> 7) in the BASE array which makes the IS_X()
function in the std_logic_arith fail.
Std_Logic (std_logic_vector) was historically known as MVL-9 donated by
Synopsys and has 9 values not 7.
> From std_logic_1164.vhdl:
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
type STD_ULOGIC_VECTOR is array (NATURAL range<>) of STD_ULOGIC;
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
The gist of this is that the enumeration indexes should go from leftmost to
leftmost+8. Where 'U' is leftmost and std_ulogic would be initialized to
leftmost unless a default value is provided. The leftmost index would be like
either 0 or 1 depending on the VHDL analyzer implementation language. You're
going to see at least an 8 for a value.
There can be valid reasons to count from 0, as in for instance characters,
where you then don't have to promote them by 1 to use indexes for character
display (e.g. 'A', NUL).
ghdl -r fp_tb --stop-time=10us --wave=fp_tb.ghw
../../../src/synopsys/std_logic_arith.vhdl:2024:16:@0ms:(assertion
warning): CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, and it has been converted to 0.
< more of similar warnings>
./fp_tb:error: bound check failure at
../../../src/synopsys/std_logic_arith.vhdl:334
./fp_tb:error: simulation failed
/usr/lib/ghdl/bin/ghdl: compilation error
I didn't follow your regime exactly and didn't get these warnings and errors.
First I copied the necessary files locally and compiled a minimal XilinxCoreLib
library, which required some modifications to the ISE 13.2 library source:
diff -r1.1 bip_utils_pkg_v1_0.vhd
1c1
< -- $Id: bip_utils_pkg_v1_0.vhd,v 1.1 2011/10/05 09:35:36 david_koontz Exp $
---
-- $Id: bip_utils_pkg_v1_0.vhd,v 1.2 2011/10/05 11:31:40 david_koontz Exp $
560,561c560,563
< for i in 0 to bitsin'length-1 loop
< if bitsin(bitsin'left+i) = '1' then
---
for i in 0 to bitsin'length loop
exit when i=bitsin'length;
if bitsin(bitsin'left+i) = '1' then
574c576,578
< for i in 0 to bitsin'length-1 loop
---
for i in 0 to bitsin'length loop
exit when i=bitsin'length;
diff -r1.1 floating_point_pkg_v4_0.vhd
7c7
< -- / / Date Last Modified: $Date: 2011/10/05 09:57:59 $
---
-- / / Date Last Modified: $Date: 2011/10/05 11:31:40 $
2779c2779,2781
< for i in 0 to flt_pt_reg_type'length-1 loop
---
for i in 0 to flt_pt_reg_type'length loop
exit when i = flt_pt_reg_type'length;
These were to appease messages from ghdl during analysis:
bip_utils_pkg_v1_0.vhd:560:18:warning: universal integer bound must be numeric
literal or attribute
bip_utils_pkg_v1_0.vhd:574:18:warning: universal integer bound must be numeric
literal or attribute
floating_point_pkg_v4_0.vhd:2779:14:warning: universal integer bound must be
numeric literal or attribute
diff -r1.1 fptop.vhd
29,30c29,30
< library UNISIM;
< use UNISIM.VComponents.all;
---
--library UNISIM;
--use UNISIM.VComponents.all;
I commented out the library and use clauses for unisim, they weren't needed for
the behavioral model.
david_koontz@Macbook: ls *.vhd*
/Users/david_koontz/Desktop/fptest
bip_utils_pkg_v1_0.vhd floating_point_v4_0_xst_comp.vhd
floating_point_pkg_v4_0.vhd fp_tb.vhd
floating_point_v4_0.vhd fptest.vhd
floating_point_v4_0_consts.vhd fptop.vhd
floating_point_v4_0_xst.vhd txt_util.vhdl
These are the files other than prebuilt libraries involved in the compilation
effort. I used a ghdl-0.29 distribution on lubuntu 11.04 running under
VirtualBox:
david-koontz-VirtualBox:/mnt/share/fptest% ghdl --version
GHDL 0.29 (20100109) [Sokcho edition]
Compiled with GNAT Version: 4.4.5 20100909 (prerelease)
GCC back-end code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2010 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
I generated a simple discrete script to analyze and simulate:
david_koontz@Macbook: more script
ghdl -a --std=93 --ieee=synopsys --work=xilinxcorelib bip_utils_pkg_v1_0.vhd
ghdl -a --std=93 --ieee=synopsys --work=xilinxcorelib
floating_point_v4_0_consts.vhd
ghdl -a --std=93 --ieee=synopsys --work=xilinxcorelib
floating_point_pkg_v4_0.vhd
ghdl -a --std=93 --ieee=synopsys --work=xilinxcorelib
floating_point_v4_0_xst_comp.vhd
ghdl -a --std=93 --ieee=synopsys --work=xilinxcorelib floating_point_v4_0.vhd
ghdl -a --std=93 --ieee=synopsys --work=xilinxcorelib
floating_point_v4_0_xst.vhd
ghdl -a --std=93 --ieee=synopsys txt_util.vhdl
ghdl -a --std=93 --ieee=synopsys fptest.vhd
ghdl -a --std=93 --ieee=synopsys fptop.vhd
ghdl -a --std=93 --ieee=synopsys fp_tb.vhd
ghdl -e --std=93 --ieee=synopsys fp_tb
ghdl -r fp_tb --stop-time=10us --wave=fp_tb.ghw
All the 32 bit buses were always zero, the clk was running the model was
introducing stimulus from the looks of things, but it was running.
david-koontz-VirtualBox:/mnt/share/fptest% !so
source script
fptop.vhd:120:1:warning: component instance "my_test" is not bound
fptop.vhd:51:14:warning: (in default configuration of fptop(behavioral))
./fp_tb:info: simulation stopped by --stop-time
The warnings were due to the architecture not being specified. The simulation
stopped after 10 usec.
I didn't have access to the ISE 11.1 you used, and with a bandwidth cap and
having just downloaded 13.2, I'm not inclined to download another version just
to get the XilinxCoreLib and Unisim libraries sources to match yours. I'd
consider the modifications I made to the iteration schemes to be less than
ideal, and I'd search for something that told me the changes were necessary.
That the Xilinx source has a few of these makes you wonder who's right.
I can't help but wonder what's going on in your IEEE libraries (or ghdl) that
you were getting those warnings and error, but have no visibility into the
problem from here. I also couldn't elaborate with an mcode version and
couldn't successfully use ieee=synopsys when analyzing
floating_point_v4_0_xst_comp.vhd:
floating_point_v4_0_xst.vhd:369:160: primary unit "std_logic_arith" not found in library
"ieee"
And the cf file showed it was included. Something else I'm too lazy to check
at 2:30 AM.
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