Ok
The sdf comes one step later.
It looks like a problem in RAM16BWER now.
rm -rf work
mkdir work
ghdl -i *.vhd
ghdl -i --work=simprim /opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/*.vhd
ghdl -i --work=simprim
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/mti/*.vhd
ghdl -i --work=simprim
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/*.vhd
ghdl -m -g -Psimprim -Wa,--32 -Wl,-m32 --warn-no-vital-generic
--ieee=synopsys -fexplicit tb_lm_cpu
../../../src/vital2000/timing_b.vhdl:196:15:warning: procedure
"vitalerror" is never referenced
../../../src/vital2000/timing_b.vhdl:217:15:warning: procedure
"vitalerror" is never referenced
../../../src/vital2000/prmtvs_b.vhdl:1041:15:warning: function "toedge"
is never referenced
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:277:5:
VITAL scalar timing type expected
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:278:5:
VITAL scalar timing type expected
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:279:5:
VITAL scalar timing type expected
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:283:5:
VITAL scalar timing type expected
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:287:5:
VITAL scalar timing type expected
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:288:5:
VITAL scalar timing type expected
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:289:5:
VITAL scalar timing type expected
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/X_RAMB16BWER.vhd:293:5:
VITAL scalar timing type expected
On 12/30/2011 01:59 AM, David Koontz wrote:
On Dec 30, 2011, at 8:41 AM, René Doß wrote:
Hallo,
my functional simulation runs but on my FPGA I get trouble. Now I want to
research the mistake.
For this I want to start a post fitting simulation.
I have in the subdirectory /ise/netgen/map all files what I need. the sdf file
and the lm_cpu_map.vhd.
ghdl -i *.vhd
ghdl -i --work=simprim /opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/*.vhd
ghdl -i --work=simprim
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/mti/*.vhd
ghdl -i --work=simprim
/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/src/simprims/primitive/other/*.vhd
ghdl -m -g -Psimprim -Wa,--32 -Wl,-m32 --warn-no-vital-generic --ieee=synopsys
-fexplicit --sdf=/.=lm_cpu_map.sdf tb_lm_cpu
ghdl: unknown option '--sdf=/.=lm_cpu_map.sdf' for command '-m'
make: *** [all] Error 1
How is the correct command line for the integration of sdf file?
ghdl --run-help
...
--sdf=[min=|typ=|max=]TOP=FILENAME
annotate TOP with SDF delay file FILENAME
...
Loading an sdf file occurs at run time, which also tells you a model won't run
as a standalone program with SDF delays loaded from an SDF file. You could
write something to produce (a) configuration statement(s) from SDF and
configure a VITAL compliant model overloading generics conveying delay values.
Back annotating in the simulator can add delays without needing a VITAL
compliant model.
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