I have been trying hard to get rid of the error message
"bound check failed (#9)" without any success, so here
goes the request for help:
below is the code for an ALU, based on Hennessy&Patterson's MIPS.
simulation breaks, SOMETIMES, at the LUI clause of the case.
All other clauses passed several tests. The ASSERT at the
bottom prints the results correctly. Further down is the code
where the ALU instance is embedded.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all; -- regXX is std_logic_vector(XX downto 0)
entity alu is
generic (ALU_LATENCY: time := 10 ns);
port(clk,rst: in std_logic;
A, B: in reg32;
C: out reg32;
LO: out reg32;
HI: out reg32;
zero: out std_logic;
move_ok: out std_logic;
fun: in t_alu_fun;
shamt: in reg5);
end alu;
architecture functional of alu is
signal reg_shamt : reg5;
begin
U_alu: process (A,B,fun,shamt)
variable i_C : reg32;
variable i_diff,i_summ : reg32;
variable i_prod : reg64;
variable i_quoc,i_mod : reg32;
variable i_move_ok : std_logic := 'L';
--variable i_C24 : std_logic_vector(31 downto 0);
--variable i_C32 : std_logic_vector(31 downto 0);
begin
i_diff := std_logic_vector(signed(A) - signed(B));
i_summ := std_logic_vector(signed(A) + signed(B));
i_prod := std_logic_vector(signed(A) * signed(B));
case fun is
when opMULT => i_lo := i_prod(31 downto 0);
i_hi := i_prod(63 downto 32);
when opMULTU => i_lo := i_prod(31 downto 0);
i_hi := i_prod(63 downto 32);
when opADD => i_C := i_summ;
when opADDU => i_C := std_logic_vector(unsigned(A) + unsigned(B));
when opSUB => i_C := i_diff;
when opSUBU => i_C := std_logic_vector(unsigned(A) - unsigned(B));
when opAND => i_C := A and B;
when opOR => i_C := A or B;
when opXOR => i_C := A xor B;
when opNOR => i_C := A nor B;
when opSLT => i_C := x"0000000" & b"000" & i_diff(31);
when opSLTU => i_C := x"0000000" & b"000" & i_diff(31);
when opLUI => i_C := x"0000000"; -- WORKS OK but is wrong
-- ALL these are failed attempts ---------------------------
--i_C := B(15 downto 0) & x"0000";
--reg_shamt <= b"10000";
--i_C := reg32(shift_left(B, reg_shamt));
--i_C(31 downto 16) := reg32(unsigned(B(15 downto 0));
--i_C(15 downto 0) := (OTHERS => '0');
--i_C32 := (31=>B(15),30=>B(14),29=>B(13),28=>B(12),
-- 27=>B(11),26=>B(10),25=>B(09),24=>B(08),
-- OTHERS=>'0');
--i_C24 := (23=>B(07),22=>B(06),21=>B(05),20=>B(04),
-- 19=>B(03),18=>B(02),17=>B(01),16=>B(00),
-- OTHERS=>'0');
--i_C := i_C32 or i_C24;
--i_C := (31=>B(15),30=>B(14),29=>B(13),28=>B(12),
-- 27=>B(11),26=>B(10),25=>B(09),24=>B(08),
-- 23=>B(07),22=>B(06),21=>B(05),20=>B(04),
-- 19=>B(03),18=>B(02),17=>B(01),16=>B(00),
-- OTHERS=>'0');
--i_C(31):=B(15); i_C(30):=B(14); i_C(29):=B(13); i_C(28):=B(12);
--i_C(27):=B(11); i_C(26):=B(10); i_C(25):=B(09); i_C(24):=B(08);
--i_C(23):=B(07); i_C(22):=B(06); i_C(21):=B(05); i_C(20):=B(04);
--i_C(19):=B(03); i_C(18):=B(02); i_C(17):=B(01); i_C(16):=B(00);
--i_C(15):='0'; i_C(14):='0'; i_C(13):='0'; i_C(12):='0';
--i_C(11):='0'; i_C(10):='0'; i_C(09):='0'; i_C(08):='0';
--i_C(07):='0'; i_C(06):='0'; i_C(05):='0'; i_C(04):='0';
--i_C(03):='0'; i_C(02):='0'; i_C(01):='0'; i_C(00):='0';
assert false report "alu: " &
"A="& SLV32HEX(A) &" ["& natural'image(operation) &"] B="&
SLV32HEX(B) &" ="& SLV32HEX( i_C ) severity note;
when others => i_C := i_summ;
end case;
C <= i_C;
if i_C = x"00000000" then zero <= '1'; else zero <= '0'; end if;
end process U_alu;
end functional;
-- ----------------------
-- CPU core, EXEC stage -------------------
U_ALU: alu generic map(0 ns)
port map(clk,rst,
alu_inp_A, alu_inp_B, result, LO, HI,
alu_zero, alu_move_ok, EX_oper, EX_shamt);
U: process(alu_inp_A, alu_inp_B, EX_oper, result)
begin
assert false report "alu: " &
"A="& SLV32HEX(alu_inp_A) &" ["& natural'image(t_alu_fun'pos(EX_oper))
&"] B="& SLV32HEX(alu_inp_B) &" ="& SLV32HEX(result) severity note;
--BUG
end process U;
EX_wreg <= '1' when (EX_move = '1' and alu_move_ok = '0') else
EX_wreg_pre; -- movz,movn, move/DO_NOT move
PIPESTAGE_EX_MM: reg_EX_MM generic map (0 ns)
port map (clk,rst, EX_MM_ld,
EX_a_rt,MM_a_rt, EX_a_c,MM_a_c, EX_wreg,MM_wreg,
EX_muxC,MM_muxC, EX_aVal,MM_aVal, EX_wrmem,MM_wrmem,
EX_A,MM_A, alu_fwd_B,MM_B,
result,MM_result, HI,MM_HI, LO,MM_LO,
EX_pc_p8,MM_pc_p8);
-- end of EXEC stage -----------------------------------------
and this is the simulation log just prior to it breaking down.
The ALU operands are correct, and so is the result:
core.vhd:681:5:@5975ns:(assertion note): alu: A=00000000 [27] B=00002d00
=00000000
core.vhd:681:5:@5975ns:(assertion note): alu: A=00000000 [27] B=00002d00
=2d000000
./tb_if:error: bound check failed (#9)
./tb_if:error: simulation failed
I thought the problem might be at the input of PIPESTAGE_EX_MM: reg_EX_MM()
so I added, out of desperation, a cast at the "result" parameter, and then:
PIPESTAGE_EX_MM: reg_EX_MM generic map (0 ns)
port map (clk,rst, EX_MM_ld,
EX_a_rt,MM_a_rt, EX_a_c,MM_a_c, EX_wreg,MM_wreg,
EX_muxC,MM_muxC, EX_aVal,MM_aVal, EX_wrmem,MM_wrmem,
EX_A,MM_A, alu_fwd_B,MM_B,
reg32(result),MM_result, HI,MM_HI, LO,MM_LO,
EX_pc_p8,MM_pc_p8);
******************* GHDL Bug occured ****************************
Please report this bug on http://gna.org/projects/ghdl
GHDL release: GHDL 0.29 (20100109) [Sokcho edition]
Compiled with GNAT Version: 4.4.5
In directory: /home/roberto/cMIPS/
Command line:
/usr/lib/ghdl/libexec/gcc/i486-linux-gnu/4.3.4/ghdl1 -fexplicit
-P/usr/lib/ghdl/lib/gcc/i486-linux-gnu/4.3.4/vhdl/lib//v93/std/
-P/usr/lib/ghdl/lib/gcc/i486-linux-gnu/4.3.4/vhdl/lib//v93/synopsys/ -quiet
-o core.s core.vhd
Exception TYPES.INTERNAL_ERROR raised
Exception information:
Exception name: TYPES.INTERNAL_ERROR
Message: translation.adb:9090
Call stack traceback locations:
0x80da0b6 0x80fc870 0x80fcd11 0x80fea9a 0x8104baf 0x8106b73 0x810a4db
0x810be44 0x810c6ec 0x8111733 0x805b280 0x804f50f
******************************************************************
Execution terminated by unhandled exception
Exception name: TYPES.INTERNAL_ERROR
Message: translation.adb:9090
Call stack traceback locations:
0x80da0b6 0x80fc870 0x80fcd11 0x80fea9a 0x8104baf 0x8106b73 0x810a4db
0x810be44 0x810c6ec 0x8111733 0x805b280 0x804f50f
/usr/lib/ghdl/bin/ghdl: compilation error
I checked, several times, that the parameters are of the right kind
(in/out) and width (reg32).
Any suggestions are most welcome.
Roberto
--
Roberto Hexsel - [email protected]
http://www.inf.ufpr.br/roberto [email protected]
"facts can speak for themselves with overwhelming precision" J.Conrad
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