On 31 May 2013, at 9:37 AM, Jon Taylor <[email protected]> wrote:

> Thanks for the tip.  What should I use as a value to enable an infinite 
> stop-delta?  Zero?
> 

The purpose of delta simulation cycles is to emulate concurrent execution 
leading to signal updates not to enable synthetic programming.

A look through the LRM(s) will show that  there is nothing that implies a limit 
to the number of delta cycles.  You will find that ghdl does impose a limit 
based on the expressible range in a natural (half the range of an integer). The 
comparison is >=, so setting --stop-delta to 0 won't work.  The delta counter 
gets set to zero after time next is incremented.

grt-processes.adb, 986:

         if Current_Delta >= Stop_Delta then
            Error ("simulation stopped by --stop-delta");
            exit;
         end if;

The reasons for placing limits in the first place would be to prevent code from 
never completing (which you are trying to overcome) or to prevent running out 
of memory by dynamic elaboration (subprogram calls which can be called 
recursively).

Historically all early VHDL simulators had delta cycle maximums (see Re: What 
is delta simulation time?).  I'm surprised ghdl's is as high as it is, if I 
recall correctly the original Modelsim had it's set to 99.  It was common to 
have the ability to report delta cycle statistics to allow users to learn to 
program better VHDL models, using a delta cycle count for description 
optimization feedback.

A solution might be to use a foreign subprogram call containing the unbound 
loop or programming in another language or implementation.  If you have the 
capacity to compile ghdl you could alter it to selective disable stop-delta, 
the feature doesn't otherwise appear to be widely needed. 

Despite any hype to the contrary VHDL is not particularly suitable to general 
purpose programming and an infinite number of delta cycles doesn't represent 
hardware described in VHDL's signal object paradigm using discrete simulation 
time advancement  and if you were to recast your code as a signal driven 
hardware model you'd still be up against time'HIGH.

You could note that IEEE Std 1076-1987 doesn't contain the word delta.  There 
is no expectation someone would write  zero simulation time hardware models.  


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