You still need to generate the stimulus, ie the input signals. This is usually done in a test bench, ie a separate vhdl file. Den 11/07/2013 10.26 skrev "Christiano" <[email protected]>:
> Hi, i'm learning vhdl, and have installed Ghdl from this site: > > http://ghdl.free.fr/site/pmwiki.php?n=Main.Download > > Windows Installer version. > > Ok. I write this code below: > > library ieee;use ieee.std_logic_1164.all; > entity dff is > port( d, clk, rst: in std_logic; > q: out std_logic);end dff; > architecture behaviour of dff isbegin > process(rst,clk) > begin > if(rst='1') then > q <= '0'; > elsif(clk'event and clk='1') then > q <= d; > end if; > > end process;end behaviour; > > And do this commands: > > ghdl -a a.vhdl > ghdl -e dff > ghdl -r dff > > The problem, is that the program stay in infinite at a last command. > [image: Inline image 1] > He is processing forever in last command. > What did I do wrong? > I have tested in Linux, and working there. > > Thank You! > > > _______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss > >
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