On 29 Nov 2013, at 5:39 am, Adrien Prost-Boucle <[email protected]> wrote:
> - The genarated circuits are intended to be synthesizable (and I > synthesized many other generated apps, analyzed hardware resource usage, > built resource usage estimators in the HLS tool, successfully executed > the designs on FPGA). So I don't generate wait statements, it's too easy > to make something not synthesizable with these. I was speaking of equivalent processes to the concurrent statements, which is how they get simulated. Not implying something you specify in your design description. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
