> speaking of trolls, they go along well with nazis, > so just go ahead, take the VHDL parser and make it re-emit source > code according to your personal tastes :-)
And make it read Verilog too ;-) I don't personally have an interest in this but I think many people would love to have it: a single free HDL simulator that handles both VHDL and Verilog. What would be the cost of building a new parser/front-end for Verilog, that would natively fit with current GHDL-generated libs? Best regards, Adrien _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
