On Sun, 2014-01-19 at 07:43 -0500, Adam Jensen wrote: > On Fri, 17 Jan 2014 14:08:32 -0500 > Adam Jensen <[email protected]> wrote: > > > $ gdb ./dlx_test_behaviour
> Program received signal SIGSEGV, Segmentation fault. > 0x00000000004299ac in work__dlx__ARCH__behaviour__interpreter__PROC > (INSTANCE=<error reading variable: Cannot access memory at address > 0x80073bd88>) at dlx-behaviour.vhdl:143 143 mem_enable <= '0' > 0x80073bd88>after Tpd_clk_out; > 142 data := d; > 143 mem_enable <= '0' after Tpd_clk_out; > 144 end bus_read; One thought : try 142 data := d; 143 mem_enable <= '0'; 144 end bus_read; does it fail in the same way, or is the delayed assignment significant? - Brian _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
