Indeed it is what people has to do. But we don't always know in advance the number of iterations. Oftenly ze have to use the xyw signal asserted somewhere else.
-----Original Message----- From: Ghdl-discuss [mailto:[email protected]] On Behalf Of [email protected] Sent: mardi 29 juillet 2014 09:26 To: GHDL discuss list Subject: Re: [Ghdl-discuss] restart simulation Le 2014-07-29 00:41, Patrick Pouget a écrit : > An alternative for the second question: > > In general there is a clock genration inside the test. That means there > is a > wait instruction. > > By writing something like > > Process > If xyz = '0' > Wait 10nS; > Else > Wait; > (some syntax has been omited for clarity) > > The simulation quits because there are not more events I use the same principle, yet with one indirection, in http://ygdes.com/GHDL/clk/clk_exemple.vhdl This is less confusing that a "severity failure" :-) yg _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
