On 08/11/14 13:41, Adrien Prost-Boucle wrote: >> Hi, >> >> With at least the versions 0.31 and 0.32 of GHDL, I have some VHDL >> designs for which simulation is extremely slow. By "extremely", I mean 1 >> cycle per minute. The same VHDL code is simulated at at least 1000 >> cycles/s with Xilinx's simulator.
Hi, We are using GHDL for a validation of a large SoC project. On version 0.31, we are experiencing a slowdown of about 570 times(!). It takes over 7hrs to simulate 200uS of simulator time. The same simulation results are generated. Here is 0.31 on Mac OS X, gcc version (mcode is exactly the same speed): ds-mac-mini:cpusim jeff$ time ./cpu_ctb --stop-time=200us --wave=foo.ghw CPU tests passed DDR Init GDB Stub for HS-2J0 SH2 ROM changeset: 958:fefcfe583a27\n\nbuild: Fri Nov 7 20:42:11 JST 2014\n\n$T0500:00000000;./cpu_tb:info: simulation stopped by --stop-time real 375m21.591s user 373m1.131s sys 1m20.614s And here is 0.29, mcode Ds-Mac-mini:cpusim jeff$ time ./cpu_ctb --stop-time=200us --wave=foo.ghw CPU tests passed DDR Init GDB Stub for HS-2J0 SH2 ROM changeset: 958:fefcfe583a27\n\nbuild: Fri Nov 7 16:07:07 JST 2014\n\n$T0500:00000000;ghdl:info: simulation stopped by --stop-time real 0m39.470s user 0m35.652s sys 0m5.533s The simulation is mixed C and VHDL, using std.textio for interprocessor communication (since mcode can't do mixed mode). We can't release the design yet (it will be open as soon as the chip with the core tapes out), but I will try and make a minimal sample. We wonder if it has to do with the overhead of textio. J. > > Hello, > > thank you very much for the reproducer, that's very useful. > I plan to work on performance issues for the next release, so your mail > is very welcome. > > From a preliminary analysis, the issue is due to concatenation. Code > generated for concatenations could be improved! > > Stay tuned. > > Regards, > Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
