On 15/05/15 13:13, melvin davis wrote:
Hello,
I am Melvin Davis. I am an Electronics student. I do love to program. I
liked this project. I wish to contribute to it. I have experience C/C++
and some other languages like Go, Java, Python etc.,(which is not useful
I guess). Also I did some projects with FPGA. Looking forward to hear
from you guys.
Hello,
first, do not hesitate to subscribe to this mailing list. The traffic
is rather low and you won't be spammed.
All contributions are welcome!
You can start by adding new features, fixing bugs (see tickets on
sourceforge), improving documentation, creating packages for
distributions...
Depending on your experience and knowledge, I can suggest a few
ideas for new features or improvements:
- it is currently possible to use LLVM as a jit engine, but the
build process is not explicit. The configure script and the
Makefile must be modified for that. Then we need to check
how LLVM optimize the code (I am not sure that optimization
passes are correctly selected)...
This has a strong link with LLVM.
- it would be nice to offer python interfaces. At two levels:
* a simulation interface: using Python to create testbench and
having a good way to drive and check VHDL designs from Python.
* a semantic interface: once VHDL code is analyzed, being able
to analyze it from Python, pretty printing in Python...
Strong link with Python (or another scripting language)
- There are missing VHDL 2008 features, like sequential signal
assignments...
Maybe that's the hardest part, as you need to deeply understand
VHDL and GHDL.
- Better integration with tools like gtkwave
- CLI during simulation
- I think it would be interesting to connect GHDL with an IDE.
First, to do syntax colouring but also to handle references.
Regards,
Tristan.
_______________________________________________
Ghdl-discuss mailing list
[email protected]
https://mail.gna.org/listinfo/ghdl-discuss
