Hallo,

I would use the interface to C language. Now I have used two procedure.
The call of procedure works.
First I can use only variables in the vhdl side. Why I can not use signal?

The values comes not correct to the C function. What is wrong?



red@linux-k4o7:~/ghdl> make
rm -rf work
mkdir work
ghdl -a  --work=work --workdir=work sim_pkg.vhd
gcc -c -fPIC sim.c -o sim.o
ghdl -a  --work=work --workdir=work tb_cosim.vhd
ghdl -e  -Wl,sim.o --ieee=synopsys -fexplicit --workdir=work -Pwork tb_cosim
ghdl -r tb_cosim  --wave=tbencha.ghw --stop-time=100ns
house: -1581548128
street: -1581548128
house: -1581548128
street: -1581548128
house: -1581548128
street: -1581548128
house: -1581548128
street: -1581548128
house: -1581548128
street: -1581548128
./tb_cosim:info: simulation stopped by --stop-time
red@linux-k4o7:~/ghdl> make
rm -rf work
mkdir work
ghdl -a  --work=work --workdir=work sim_pkg.vhd
gcc -c -fPIC sim.c -o sim.o
ghdl -a  --work=work --workdir=work tb_cosim.vhd
ghdl -e  -Wl,sim.o --ieee=synopsys -fexplicit --workdir=work -Pwork tb_cosim
ghdl -r tb_cosim  --wave=tbencha.ghw --stop-time=100ns
house: -433776384
street: -433776384
house: -433776384
street: -433776384
house: -433776384
street: -433776384
house: -433776384
street: -433776384
house: -433776384
street: -433776384
./tb_cosim:info: simulation stopped by --stop-time
red@linux-k4o7:~/ghdl>




all:


        rm -rf work
        mkdir work

                
        ghdl -a  --work=work --workdir=work sim_pkg.vhd
        gcc -c -fPIC sim.c -o sim.o
        
        
        
        ghdl -a  --work=work --workdir=work tb_cosim.vhd


        ghdl -e  -Wl,sim.o --ieee=synopsys -fexplicit --workdir=work -Pwork 
tb_cosim

#       ghdl -r tb_lm_cpu  
        ghdl -r tb_cosim  --wave=tbencha.ghw --stop-time=100ns
#       ghdl -r tbench --disp-tree=inst --wave=tbench.ghw 

#       ghdl -r tb_lm_cpu  


view:
        gtkwave tbencha.ghw a.sav


post:
        rm -rf work
        mkdir work
        ghdl -i ../ise601/netgen/synthesis/MAIS_soc_synthesis.vhd
        ghdl -i ../rtl/tb_MAIS.vhd
        ghdl -i --work=unisim /opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/*.vhd
        ghdl -i --work=unisim 
/opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/primitive/*.vhd



        ghdl -m  -g  -Punisim -Psimprim --warn-unused --ieee=synopsys 
-fexplicit  tb_lm_cpuvi
        ghdl -r tb_lm_cpu --disp-tree=inst --wave=tbench.ghw --stop-time=50us
#include <stdio.h>


void street(int number)
{
   printf("street: %d\n",number);
}        


void house(int number)
{
   printf("house: %d\n",number);
}        

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


package sim_pkg is



  procedure house ( reg : out integer );
  attribute foreign of house :
    procedure is "VHPIDIRECT house"; 


  procedure street ( reg : out integer );
  attribute foreign of street :
    procedure is "VHPIDIRECT street";   
end;


package body sim_pkg is


  procedure house (reg : out integer)  is
  begin
    assert false report "VHPI" severity failure;
  end house;

  procedure street (reg : out integer)  is
  begin
    assert false report "VHPI" severity failure;
  end street;
    
end sim_pkg;
--------------------------------------------------------------------------------
-- Company:      Dossmatik GmbH
-- Create Date:   21:08:31 05/17/2011

-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench 
-- test for VHPI
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.sim_pkg.all;


entity tb_cosim is
end tb_cosim;

architecture behavior of tb_cosim is



  -- Clock period definitions

  constant board_clk_period : time := 20 ns;

  signal a: integer:= 0;
  signal b: integer:= 0;
  signal board_clk: std_logic;
begin


 
  process (board_clk)
  variable a1: integer;
  begin 
    if rising_edge(board_clk) then
      a1:=a;
      street(a1);
      a<=a+1;
    end if;
  end process;
  

  process (board_clk)
  variable b1: integer;
  begin 
   if rising_edge(board_clk) then
     b1:=b;
     house(b1);
     b<=b+1;
   end if;
  end process;





  -- Clock process definitions
  board_clk_process : process
  begin
    board_clk <= '0';
    wait for board_clk_period/2;
      board_clk <= '1';
    wait for board_clk_period/2;
  end process;


  end;
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